82595FX Datasheet, PDF (7/54 Pages) Intel Corporation – ISA BUS HIGH INTEGRATION ETHERNET CONTROLLER

82595FX
2 1 ISA Bus Interface (Continued)
Symbol
Pin
No
Type
Name and Function
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
81 I O DATA BUS This is the data interface between the 82595FX and the host
83
system This data is buffered by one (8-bit design) or two (16-bit design)
85
internal transceivers
87
88
90
92
94
60
58
56
54
53
51
49
47
AEN
24
I
ADDRESS ENABLE Active high signal indicates a DMA cycle is active
SMEMR
20
I
MEMORY READ for system memory accesses below 1 Mbyte Active low
SMEMW
21
I
MEMORY WRITE for system memory accesses below 1 Mbyte Active
low
IOR
22
I
IO READ Active low
IOW
23
I
IO WRITE Active low
IOCS16
45
O IO CHIP SELECT 16 Active low open drain output which indicates that
an IO cycle access to the 82595FX solution is 16-bit wide Driven for IO
cycles to the local memory or to the 82595FX
IOCHRDY
42
O IO CHANNEL READY Active high open drain output When driven low it
extends host cycles to the 82595FX solution
SBHE
37
I
SYSTEM BUS HIGH ENABLE Active low input indicates a data transfer
on the high-byte (D8 – D15) of the system bus (a 16-bit transfer) This pin
also determines if the 82595FX is operating in an 8- or 16-bit system upon
initialization
INT0
INT1
INT2
INT3
INT4
INT5
INT6
INT7
29
O 82595FX INTERRUPT 0 – 7 One of these 8 pins is selected to be active
30
one at a time (the other seven are in Hi-Z state) by configuration These
31
active high outputs serve as interrupts to the host system
32
33
34
35
36
RESET DRV 19
I
RESET DRIVE Active high reset signal
7