82595FX Datasheet, PDF(28/54 Page) Intel Corporation – ISA BUS HIGH INTEGRATION ETHERNET CONTROLLER

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82595FX Datasheet, PDF (28/54 Pages) Intel Corporation – ISA BUS HIGH INTEGRATION ETHERNET CONTROLLER

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82595FX

7 3 Automatic Retransmission on

Collision

The 82595FX performs automatic retransmission

when a collision is experienced within the first slot

time of the transmission with no intervention by the

CPU The 82595FX performs jamming exponential

backoff and retransmission attempts as specified by

the IEEE 802 3 spec The 82595FX reaccesses its

local memory automatically on collision This allows

the 82595FX to retransmit up to 15 times after the

initial collision with no CPU interaction

The 82595FX reaccesses the data in its transmit

buffer by simply resetting the value of its Current

Address Register back to the value of the Base Ad-

dress Register (the beginning of the XMT block) and

repeating the DMA process to access the data in the

transmit buffer again Once it regains access to the

link retransmission is attempted When Transmit

Chaining is utilized the process for retransmission is

exactly the same Only the current frame in the

chain will be retransmitted since the Base Address

frame

8 0 FRAME RECEPTION

The 82595FX implements a recyclable ring buffer

DMA structure to support the reception of back to

back incoming RCV frames with minimal CPU over-

head The structure of the RCV frames in memory is

optimized to allow the CPU to process each frame

with as few software processing steps as pos-

sible The frame format is arranged so that all of the

required infomation for each frame (status size

etc ) is located at the beginning of the frame

8 1 82595FX RCV Memory Structure

The 82595FX RCV memory structure for a 16-bit in-

terface is shown in Figure 8-1 Figure 8-2 shows this

structure for the 8-bit interface Once an incoming

frame passes the 82595FXâs address filtering the

82595FX deposits the frame into the RCV Data field

of the RCV Memory Structure The fields which pre-

cede the RCV Data field Event Status Byte Count

Next Frame Pointer and the Event field of the fol-

lowing frame are updated upon the end of the frame

after all of the incoming data has been deposited in

the RCV Data field If Receive Concurrent Process-

ing is enabled the CPU processes the receive frame

without the entire frame being deposited by the

82595FX to the RCV Data Field The 85295FX

along with the software driver determines the por-

tion of the frame being copied to host memory be-

fore the rest of that frame is copied to local memory

An interrrupt is asserted by the 82595FX (EOF) after

frame reception has been completed

If the 82595FX is configured to Discard Bad Frames

it will discard all incoming errored frames by reset-

ting its DMA Current Address Register back to the

value of the Base Address Register and not updat-

ing any of the fields in the RCV frame structure This

area will now be reused to store the next incoming

frame

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