82595FX Datasheet, PDF (19/54 Pages) Intel Corporation – ISA BUS HIGH INTEGRATION ETHERNET CONTROLLER

82595FX
4 5 Serial EEPROM Interface
A Serial EEPROM a Hyundai HY93C46 or equiva-
lent IC stores configuration data for the 82595FX
The use of an EEPROM enables 82595FX designs
to be implemented without jumpers (the use of jump-
ers to select IO windows is optional ) The port inter-
face to the serial EEPROM provides both configura-
tion and Plug N’ Play information access Plug N’
Play allows peripheral functions to be added to a PC
(such as adapter cards) without the need to individu-
ally configure each parameter (e g Interrupt IO Ad-
dress etc) Information describing system resources
are contained within the 82595FX configuration reg-
isters This allows Auto-configuration software
which is usually contained in the BIOS or O S to
identify system resource usage identify conflicts
and automatically re-configure the 82595FX
The 82595FX automatically accesses Register 0 of
the EEPROM upon a RESET in ISA Bus Interface
mode Register 0 contains the information that the
82595FX must be configured to allow CPU
accesses to it (IO Mapping Window FLASH Detect
Enable Auto I O Enable Boot EPROM FLASH
Window Host Bus Width and Plug N’ Play Enable)
following a system boot The format for EEPROM
Register 0 is shown in Figure 4-1 Note that all 0’s
are assumed to be reserved In the case where an
EEPROM is either unprogrammed (each bit defaults
to a 1) or completely erased (all 0’s) the 82595FX
will default to IO Address 300h
Word0 Bit 1 the Word 1 Enable bit is asserted to
enable the read of EEPROM Word 1 during reset
This bit is active high
NOTE
If Word 1 of the EEPROM is not to be read
during a reset software must wait 200 ms af-
ter the reset is issued before accessing the
82595FX as was the case on all versions of
the 82595 If Word 1 is to be read during a
reset software must wait 400 ms after reset
before accessing the part During this
‘‘blackout’’ period the part will not respond
to accesses on the ISA bus
Word 0 Bit 8 is the Flash Present bit This bit is
active low to indicate the presence of flash memory
as in the 82595FX B-3 The functionality of the bit is
changed from the 82595FX B-2 and prior versions
Word 0 Bit 9 is the Auto-Negotiation or A-N Enable
bit for the negotiation process at boot time The bit is
active high
Word 1 of the EEPROM is used to store the INT
Select value to which the part will default on reset
The mapping from INT Select to IRQ is explained
later in this document The value stored in bits 0
through 2 of word 1 of the EEPROM is loaded into
the INT Select register of the 82595FX bank 1 reg-
ister 2 bits 0 through 2 on any hardware or software
reset The reading of Word 1 on reset is enabled
when bit 1 of word 0 of the EEPROM is set If this bit
is not set on reset word 1 will not be read and the
INT select register and Bad IRQ bit in bank 1 will be
initialized to zero
For additional information regarding a Plug N’ Play implementation for the 82595FX please consult the
82595FX User’s Guide and LAN595TX Specification available through your local sales representative
The latest Plug N’ Play Specification is available by Microsoft
D15
D3
D2
D1
D0
Software Reserved
INT Select
Figure 4-1 EEPROM Register 0
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
I O Mapping Window
A-N Flash
Auto-
0
En Pres
En
BT FLASH
Window
Host Word PnP
Wdth 1 En
En
Figure 4-2 EEPROM Register 1
19