82595FX Datasheet, PDF (17/54 Pages) Intel Corporation – ISA BUS HIGH INTEGRATION ETHERNET CONTROLLER

82595FX
4 1 3 IO BANK 2
The format for IO Bank 2 is shown below
7
6
5
4
3
2
1
POINTER
ABORT
COMMAND OP CODE
Disc
Bad Fr
Tx Chn
ErStp
LoopBack
Test 1
Test 2
STEPPING
Polarity
Link
LED
LED
0
0
0
0
Tx Chn
Int Md
Multi
IA
BNC
TPE
Activity
LED
0
0
Res
0
0
0
(Reserved)
No SA
Ins
Length
Enable
RX CRC
In MEM
APORT
Jabber
Disable
TPE
AUI
INDIVIDUAL ADDRESS
REGISTER 0
INDIVIDUAL ADDRESS
REGISTER 1
INDIVIDUAL ADDRESS
REGISTER 2
INDIVIDUAL ADDRESS
REGISTER 3
INDIVIDUAL ADDRESS
REGISTER 4
INDIVIDUAL ADDRESS
REGISTER 5
Turnoff
Enable
EEDO
EEDI
RCV NO RESOURCE
COUNTER
Reserved
0
0
(Resvrd)
Auto-Negotiation
Status
0
0
0
(Reserved)
0
0
0
(Reserved)
0
BC
DIS
Pol
Corr
EECS
A-N
Enable
0
0
0
TX Con
Proc En
PRMSC
Mode
Link In
Dis
Reg 0
(CMD
Reg)
Reg 1
Reg 2
Reg 3
Reg 4
Reg 5
Reg 6
Reg 7
Reg 8
EESK
Reg 9
Reg 10
Reg 11
FDX
HDX
0
0
Reg 12
Reg 13
Reg 14
Reg 15
4 2 Writing to the 82595FX
Writing to the 82595FX is accomplished by an IO
Write instruction (such as an OUT instruction) from
the host processor to one of the 82595FX registers
The 82595FX registers reside in a block of 16 con-
tiguous addresses contained within the PC IO ad-
dress space The mapping of this address block is
programmable throughout the 1 Kbyte PC IO ad-
dress map
The 82595FX registers are contained within three
banks of IO registers When writing to a particular
register the processor must first select the correct
bank (Bank 0 1 or 2) in which the register resides
Once a bank is selected all register accesses are
made in that bank until a switch to another bank is
performed Switching banks is accomplished by writ-
ing to the PTR field of Reg 0 in any bank Reg 0 is
the command register of the 82595FX and its func-
tionality is identical in each bank Once in the appro-
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