X930A Datasheet, PDF (37/38 Pages) Intel Corporation – UNIVERSAL SERIAL BUS MICROCONTROLLER

8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
Table 20. 8x930Ax3 and 8x930Ax4 Default and Extended Data Float Timings (Continued)
Sym-
bol
Parameter
Default Data Float
Timing (ns)
Compatibility Mode
(EDF# =1) (1,2,4,5)
Extended Data Float
Timing (ns)
Increased T_RHDZ1 mode
(EDF#=0) (1,3,4,5)
T_RHDZ2 Data Float After PSEN# or RD# High
T_CLK + 10 [max]
1.5 T_CLK - 5 [max]
T_RHLH2 RD# or PSEN# High to ALE High (data)
T_CLK + 10 [min]
(1.5)T_CLK - 7 [min]
T_RHLH1 PSEN# High to ALE High (inst.)
10 [min]
(0.5)T_CLK - 7 [min]
T_WHLH WR# High to ALE High
T_CLK + 10 [min]
(1.5)T_CLK - 7 [min]
T_AVDV1 Address (mux’ed) Valid to Valid Data/Inst. In (2+M+N)T_CLK - 60 [max] (1.5+M+N)T_CLK - 28 [max]
T_AVRL Address Valid to RD# or PSEN# Low
(1+M)T_CLK- 40 [min]
(0.5+M)T_CLK + 10 [min]
T_AVWL1 Address (mux’ed) Valid to WR# Low
(1+M)T_CLK- 40 [min]
(0.5+M)T_CLK + 10 [min]
T_AVWL2 Address (demux’ed) Valid to WR# Low
(1+M)T_CLK- 17 [min]
(1+M)T_CLK + 10 [min]
NOTES:
1. Worst-case numbers based on silicon data collected to date.
2. Device configured with default data float timing for fast memory interface.
3. Device configured with extended data float timing for slow memory interface.
4. The values listed are for 12 MHz. For 6 MHz, the value of T_CLK will double and will equal 166.6 ns.
5. M=0,1 is the extended ALE state; N= 0,1,2,3 is the RD#/PSEN#/WR# wait state.
Table 21. 8x930Ax3 and 8x930Ax4 Real-time Wait State AC Timing Specifications
Symbol (Parameter)
F_CLK Variable
Default Data Float Timing (ns)
(EDF#=1)
F_CLK Variable
Extended Data Float Timing (ns)
(EDF#=0)
Min
Typ
Max
Min
Typ
Max
T_RLYV (PSEN# or RD# Low to
0
Wait Setup)
0.5 T_CLK - 13
0
0.5 T_CLK - 35
T_WLYV (WR# Low to Wait Setup)
0
0.5 T_CLK - 13
0.5 T_CLK - 35
ADVANCE INFORMATION
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