X930A Datasheet, PDF (36/38 Pages) Intel Corporation – UNIVERSAL SERIAL BUS MICROCONTROLLER

8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
Table 19. AC Characteristics for 8x930Ax3 and 8x930Ax4 in Compatibility Mode
Symbol
Parameter
8x930Ax3/8x930Ax4
Compatibility Mode (ns)
(EDF# =1) (1)
T_AVLL
Address Valid to ALE Low
(0.5+M)T_CLK - 13 [min]
T_LLAX
Address Hold after ALE Low
10 [min]
T_WLWH
WR# Pulse Width
(1+N)T_CLK - 10 [min]
T_LLRL
ALE Low to RD# or PSEN# low
10 [min]
T_LHAX
ALE High to Address Hold
(1+M)T_CLK - 27 [min]
T_RLDV
RD# or PSEN# Low to Valid Data/Inst. In
(1+N)T_CLK - 30 [max]
T_RLAZ
RD# or PSEN# Low to Address Float
3 max (2)
T_RHDZ2 Data Float After PSEN# or RD# High
T_CLK + 10 [max]
T_RHLH2 RD# or PSEN# High to ALE High (data)
T_CLK + 10 [min]
T_WHLH
WR# High to ALE High
T_CLK+10 [min]
T_AVDV2 Address (demux’ed) Valid to Valid Data/Instr. In
(2+M+N)T_CLK - 38 [max]
T_AVRL
Address Valid to RD# or PSEN# Low
(1+M)T_CLK - 40 [min]
T_AVWL1 Address (mux’ed) Valid to WR# Low
(1+M)T_CLK - 40 [min]
NOTES:
1. Device configured with default data float timing for fast memory interface.
2. Typical value is 0 ns.
Table 20. 8x930Ax3 and 8x930Ax4 Default and Extended Data Float Timings
Sym-
bol
Parameter
Default Data Float
Timing (ns)
Compatibility Mode
(EDF# =1) (1,2,4,5)
Extended Data Float
Timing (ns)
Increased T_RHDZ1 mode
(EDF#=0) (1,3,4,5)
T_LLAX Address Hold after ALE Low
10 [min]
20 [min]
T_RLRH RD# or PSEN# Pulse Width
(1+N)T_CLK - 10 [min]
(1+N)T_CLK - 32 [min]
T_WLWH WR# Pulse Width
(1+N)T_CLK - 10 [min]
(1+N)T_CLK - 32 [min]
T_LLRL ALE Low to RD# or PSEN# low
10 [min]
20 [min]
T_LHAX ALE High to Address Hold
(1+M)T_CLK - 27 [min]
(0.5+M)T_CLK + 15 [min]
T_RLDV RD# or PSEN# Low to Valid Data/Inst. In
(1+N)T_CLK - 30 [max]
(1+N)T_CLK - 50 [max]
T_RHDZ1 Instruct. Float After PSEN# or RD# High
10 [max]
(0.5)T_CLK - 5 [max]
NOTES:
1. Worst-case numbers based on silicon data collected to date.
2. Device configured with default data float timing for fast memory interface.
3. Device configured with extended data float timing for slow memory interface.
4. The values listed are for 12 MHz. For 6 MHz, the value of T_CLK will double and will equal 166.6 ns.
5. M=0,1 is the extended ALE state; N= 0,1,2,3 is the RD#/PSEN#/WR# wait state.
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