X930A Datasheet, PDF (12/38 Pages) Intel Corporation – UNIVERSAL SERIAL BUS MICROCONTROLLER

8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
Table 5. Signal Descriptions (Continued)
Signal
Name
Type
Description
Alternate Function
P1.0
P1.1
P1.2
P1.5:3
P1.6
P1.7
I/O Port 1. This is an 8-bit, bidirectional I/O port with internal
pullups.
T2
T2EX
ECI
CEX2:0
CEX3/WAIT#
CEX4/A17/WCLK
P2.7:0
I/O Port 2. This is an 8-bit, bidirectional I/O port with internal
pullups.
A15:8
P3.0
P3.1
P3.3:2
P3.5:4
P3.6
P3.7
I/O Port 3. This is an 8-bit, bidirectional I/O port with internal
pullups.
RXD
TXD
INT1:0#
T1:0
WR#
RD#/A16
PLLSEL2:0
I Phase-locked Loop Select. Three-bit code selects USB —
data rate (see Table 8 on page 12).
PSEN#
O Program Store Enable. Read signal output. This output is —
asserted for a memory address range that depends on bits
RD0 and RD1 in configuration byte UCONFIG0 (see RD#).
RD#
O Read or 17th Address Bit (A16). Read signal output to
P3.7/A16
external data memory or 17th external address bit (A16),
depending on the values of bits RD0 and RD1 in configura-
tion byte UCONFIG0 (See PSEN#).
RST
I Reset. Reset input to the chip. Holding this pin high for 64 —
oscillator periods while the oscillator is running resets the
device. The port pins are driven to their reset conditions
when a voltage greater than V_IH1 is applied, whether or not
the oscillator is running. This pin has an internal pulldown
resistor which allows the device to be reset by connecting a
capacitor between this pin and V_CC.
Asserting RST when the chip is in idle mode or powerdown
mode returns the chip to normal operation.
RXD
I/O Receive Serial Data. RXD sends and receives data in
P3.0
serial I/O mode 0 and receives data in serial I/O modes 1, 2,
and 3.
SOF#
O Start of Frame. Start of Frame pulse. Active low, asserted —
for 8 states (see Table 8 on page 12 for state versus XTAL
clock) when Frame Timer is locked to USB frame timing
and SOF token or artificial SOF is detected.
T1:0
I Timer 1:0 External Clock Inputs. When timer 1:0 operates P3.5:4
as a counter, a falling edge on the T1:0 pin increments the
count.
T2
I/O Timer 2 Clock Input/Output. For the timer 2 capture mode, P1.0
this signal is the external clock input. For the clock-out
mode, it is the timer 2 clock output.
† _{The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration. If the}
chip is configured for page-mode operation, port 0 carries the lower address bits (A7:0), and port 2 car-
ries the upper address bits (A15:8) and the data (D7:0).
8
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