X930A Datasheet, PDF (20/38 Pages) Intel Corporation – UNIVERSAL SERIAL BUS MICROCONTROLLER

8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
5.4 AC Characteristics
Test Conditions: Capacitive load on all pins = 50 pF, Rise and Fall times = 10 ns, F_OSC = 6 MHz or 12 MHz
5.4.1 SYSTEM BUS AC CHARACTERISTICS
Table 11. AC Characteristics at Operating Conditions
Symbol
Parameter
CPU Frequency CPU Frequency (F_CLK) Variable
@ 12 MHz
Units
(M, N = 0)
Min
Max
T_CLK
1/(CPU Frequency)
83.33
(Typical)
ns
(1, 2)
T_LHLL
T_AVLL
ALE Pulse Width
Address Valid to ALE Low
34.66
26.66
(0.5+M)T_CLK – 7
(0.5+M)T_CLK –
17
ns (3)
ns (3)
T_LLAX
T_RLRH (5)
T_WLWH
T_LLRL (5)
T_LHAX
T_RLDV (5)
Address Hold after ALE Low
RD# or PSEN# Pulse Width
WR# Pulse Width
ALE Low to RD# or PSEN# Low
ALE High to Address Hold
RD# or PSEN# Low to Valid
Data/Instruction In
4
73.33
71.33
8
40.33
50.33
4
(1+N)T_CLK – 10
(1+N)T_CLK – 12
8
(1+M)T_CLK – 43
(1+N)T_CLK – 33
ns (4)
ns (6)
ns (6)
ns
ns (3)
ns (6)
T_RHDX (5) Data/Instruct. Hold After RD# or
0
0
ns
PSEN# High
T_RLAZ (5) RD# or PSEN# Low to Address
0
Float
0
ns
T_RHDZ1 (5)
T_RHDZ2 (5)
Instruct. Float After PSEN# High
Data Float After RD# or PSEN#
High
10
83.33
10
ns
T_CLK
ns
T_RHLH1 (5) PSEN# High to ALE High
10
10
ns
(Instruction)
T_RHLH2 (5) RD# or PSEN# High to ALE
83.33
T_CLK
ns
High (Data)
T_WHLH
T_AVDV1
WR# High to ALE High
Address (P0) Valid to Valid
Data/Instruction In
88.33
106.66
T_CLK + 5
(2+M+N)T_CLK –
63
ns
ns
(3, 6)
NOTES:
1. Refer to Table 8 on page 12 for CPU frequencies vs. XTAL1 frequencies.
2. XTAL1 frequency is ± 0.25% for full speed and ± 1.5% for low speed.
3. M= 0,1 is the extended ALE state.
4. At 50° C, T_LLAX = 8 ns
5. Specifications for PSEN# are identical to those for RD#.
6. N= 0,1,2,3 is the RD#/PSEN#/WR# wait state.
16
ADVANCE INFORMATION