X930A Datasheet, PDF (18/38 Pages) Intel Corporation – UNIVERSAL SERIAL BUS MICROCONTROLLER

8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
Table 9. DC Characteristics at Operating Conditions (Continued)
Symbol
Parameter
Min
Typical (1)
Max
Units Test Conditions
I_TL
Logical 1-to-0
Transition Current
(Port 1, 2,3)
-650
V_IN = 2.0 V
µA
R_RST
RST Pulldown
40
Resistor
225
KΩ
C_IO
I_PD
Powerdown Current
— Normal powerdown
— USB suspend
10
pF ^{FOSC = 12 MHz}
T_A = 25°C
25
50
µA
145
175
I_DL (5) Idle Mode I_CC
40
PLLSEL = 110
3MHz – FS
(in low clock mode)
100
PLLSEL = 110
12MHz – FS
mA _{(not in low clock}
mode)
30
PLLSEL = 001
3MHz – LS
55
PLLSEL = 100
6 MHz – LS
NOTE:
1. Typical values are obtained using V_CC = 5.0V, T_A = 25°C and are not guaranteed.
2. Under steady state (non-transient) conditions, I_OL must be externally limited as follows:
Maximum I_OH per port pin:10 mA
Maximum I_OL per 8-bit port:
Port 0: 26 mA
Ports 1-3: 15 mA
Maximum Total I_OL for all output pins: 71 mA
If I_OL exceeds the test conditions, V_OL may exceed the related specification. Pins are not guaranteed
to sink current greater than the listed test conditions.
3. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level
outputs of ALE and Ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the
Port 0 and Port 2 pins when these pins change from 1 to 0. In applications where capacitive loading
exceeds 100pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qualify
ALE or other signals with a Schmitt Trigger or CMOS-level input logic.
4. Capacitive loading on Ports 0 and 2 cause the V_OH on ALE and PSEN to drop below the V_CC specifica-
tion when the address lines are stabilizing.
5. The abbreviations “LS” and “FS” indicate “Low Speed” and “Full Speed,” respectively.
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