X930A Datasheet, PDF (17/38 Pages) Intel Corporation – UNIVERSAL SERIAL BUS MICROCONTROLLER

8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
5.2 DC Characteristics
Table 9. DC Characteristics at Operating Conditions
Symbol
Parameter
Min
Typical (1)
Max
Units Test Conditions
V_IL
Input Low Voltage
-0.5
(Except EA#)
0.2 V_CC – 0.1 _V
V_IL1
Input Low Voltage
0
(EA#)
0.2 V_CC – 0.3 _V
V_IH
Input High Voltage
0.2 V_CC + 0.9
(Except XTAL1, RST)
V_CC + 0.5
V
V_IH1
Input High Voltage
(XTAL1, RST)
0.7 V_CC
V_CC + 0.5
V
V_OL
Output Low Voltage
(Port 1, 2, 3)
V_OL1
V_OH
V_OH1
I_IL
Output Low Voltage
(Port 0, ALE, PSEN#,
SOF#)
Output High Voltage
(Port 1, 2, 3,ALE,
PSEN#, SOF#)
Output High Voltage
(Port 0 in External
Address)
Logical 0 Input
Current (Port 1,2,3)
V_CC – 0.3
V_CC – 0.7
V_CC – 1.5
V_CC – 0.3
V_CC – 0.7
V_CC – 1.5
0.3
0.45
1.0
0.3
0.45
1.0
–150
I_OL = 100 µA (2, 3)
V I_OL = 1.6 mA
I_OL = 3.5 mA
I_OL = 200 µA (2, 3)
V I_OL = 3.2 mA
I_OL = 7.0 mA
I_OH = -10 µA (4)
V I_OH = -30 µA
I_OH = -60 µA
I_OH = -200 µA (4)
V I_OH = -3.2 mA
I_OH = -7.0 mA
µA ^{VIN = 0.45 V}
I_LI
Input Leakage Current
(Port 0)
±10
µA ^{0.45 < VIN < VCC}
NOTE:
1. Typical values are obtained using V_CC = 5.0V, T_A = 25°C and are not guaranteed.
2. Under steady state (non-transient) conditions, I_OL must be externally limited as follows:
Maximum I_OH per port pin:10 mA
Maximum I_OL per 8-bit port:
Port 0: 26 mA
Ports 1-3: 15 mA
Maximum Total I_OL for all output pins: 71 mA
If I_OL exceeds the test conditions, V_OL may exceed the related specification. Pins are not guaranteed
to sink current greater than the listed test conditions.
3. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level
outputs of ALE and Ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the
Port 0 and Port 2 pins when these pins change from 1 to 0. In applications where capacitive loading
exceeds 100pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qualify
ALE or other signals with a Schmitt Trigger or CMOS-level input logic.
4. Capacitive loading on Ports 0 and 2 cause the V_OH on ALE and PSEN to drop below the V_CC specifica-
tion when the address lines are stabilizing.
5. The abbreviations “LS” and “FS” indicate “Low Speed” and “Full Speed,” respectively.
ADVANCE INFORMATION
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