X930A Datasheet, PDF (14/38 Pages) Intel Corporation – UNIVERSAL SERIAL BUS MICROCONTROLLER

8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
Table 6. Memory Signal Selections (RD1:0)
RD1:0
†
A17/P1.7
/CEX4/WCLK
A16/P3.7/RD#
PSEN#
WR#
Features
0 0 A17
A16
Asserted for Asserted for writes to 256-Kbyte external
all addresses all memory locations memory
0 1 P1.7/CEX4/WCLK A16
Asserted for Asserted for writes to 128-Kbyte external
all addresses all memory locations memory
1 0 P1.7/CEX4/WCLK P3.7 only
Asserted for Asserted for writes to
all addresses all memory locations
64-Kbyte external
memory
One additional port
pin
1 1 P1.7/CEX4/WCLK RD# Asserted Asserted for Asserted for all com- Compatible with
for addresses addresses patible MCS 51 mem- MCS 51 microcon-
≤ 7F:FFFFH ≥ 80:0000H ory locations
trollers
† _{RD1:0 are bits 3:2 of configuration byte UCONFIG0. Refer to figure 4-3 on page 4-5 in the 8x930Ax Uni-}
versal Serial Bus Microcontroller User’s Manual.
4.0 ADDRESS MAP
Table 7. 8x930Ax Address Map
Internal
Address
Description
Notes
FF:FFFFH
FF:0000H
External Memory: The last eight bytes of the external address range FF:XFF8H–
FF:XFFFH contain configuration byte information.
1, 2, 3
FE:FFFFH
FE:0000H
External Memory
2
FD:FFFFH
02:0000H
Reserved Addresses
4
01:FFFFH
01:0000H
External Memory
2
00:FFFFH
00:0420H
External Memory
5
00:041FH
00:0080H
On-chip RAM
5
00:007FH
00:0020H
On-chip RAM
6
00:001FH
00:0000H
Storage for R0–R7 of Register File
7, 8
NOTES:
1. Eighteen address lines are bonded out (A15:0, A16:0, or A17:0 selected during chip configuration).
2. Data in this area is accessible by indirect addressing only.
3. Eight addresses at the top of all external memory maps are reserved for current and future device
configuration byte information.
4. This reserved area returns unspecified values and writes no data.
5. Data is accessible by direct and indirect addressing.
6. Data is accessible by direct, indirect, and bit addressing.
7. The special function registers (SFRs) and the register file have separate internal address spaces.
8. Data is accessible by direct, indirect, and register addressing.
10
ADVANCE INFORMATION