82540EP Datasheet, PDF (3/46 Pages) Intel Corporation – 82540EP Gigabit Ethernet Controller

Networking Silicon — 82540EP
Revision History
Date
Apr 2002
Nov 2002
Jan 2003
Apr 2003
Oct 2003
Nov 2004
Nov 2004
July 2006
Sept 2006
Feb 2007
Sept 2007
Sept 2008
Revision
0.25
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
Notes
Initial Release
Changed document status to Intel Confidential.
Section 1.0. Replaced Block Diagram
Section 2.6. Added Table footnote
Section 4.1, 4.2, 4.3. Replaced tables
Section 5.1. Added Visual Pin Reference
Section 4.4 Removed Power Supply Characteristics; added note to I/O Char-
acteristics
Section 5.0 Replaced Pinout Diagram
Removed confidential status.
Section 1.0. Added product ordering code.
Updated Table 8 to reflect correct values for internal pull-up impedance.
Added product features to cover.
Updated signal names to match design guide and reference schematics.
Added information about migrating from a 2-layer 0.36 mm wide-trace sub-
strate to a 2-layer 0.32 mm wide-trace substrate. Refer to the section on Pack-
age and Pinout Information.
Added statement that no changes to existing soldering processes are needed
for the 2-layer 0.32 mm wide-trace substrate change in the section describing
“Package Information”.
Corrected pinout discrepancies between Tables 35 and 36.
Added LAN-disable description to the FLSH_SO signal description in Section
3.
Added industrial temperature values to “Product Features” and Table 2.
Added a note to Figure 12 clarifying the device pin 1 location.
Updated Section 5.3 “Thermal Specifications”.
Updated ball G13 description to 1.5V. Updated Figure 12 (changed G13
description to 1.5V).
Updated section 3.6 (added pull down resistor value for TEST pin).
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