82540EP Datasheet, PDF (19/46 Pages) Intel Corporation – 82540EP Gigabit Ethernet Controller

Networking Silicon — 82540EP
3.6
Test Interface Signals
3.7
3.7.1
3.7.2
Symbol
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_
TRST#
TEST
CLK_VIEW
ALTCLK_125
CLK_BYP#
HSDACP
HSDACN
PHY_TSTPT
Type
Name and Function
I
JTAG Clock.
I
JTAG TDI.
O
JTAG TDO.
I
JTAG TMS.
I
JTAG Reset. This is an active low reset signal for JTAG. This signal should be
terminated using a pull-down resistor to ground. It must not be left unconnected.
I
Factory Test Pin. For normal operation, this pin must be pulled down to ground
using a 1 K resistor.
O
Clock View. Output for GTX_CLK and RX_CLK during IEEE PHY conformance
testing. The clock is selected by register programming.
Alternate CLK125 Input. Factory use only.
I
For normal component operation, connect to VSS.
Clock Bypass Enable. Factory use only.
I
For normal component operation, no connect.
PHY High Speed Test Interface. Factory use only.
I
For normal component operation, no connect.
PHY High Speed Test Interface. Factory use only.
I
For normal component operation, no connect.
PHY Test Point. Factory use only.
I
For normal component operation, no connect.
Power Supply Connections
Digital Supplies
Symbol
VDDO
DVDD
Type
Name and Function
P
3.3 V I/O Power Supply.
P
1.5 V Digital Core Power Supply.
Analog Supplies
Symbol
AVDDH
AVDDL
Type
Name and Function
P
3.3 V Analog Power Supply.
P
2.5 V Analog Power Supply.
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