82540EP Datasheet, PDF (16/46 Pages) Intel Corporation – 82540EP Gigabit Ethernet Controller

82540EP — Networking Silicon
3.2.6
3.2.7
3.2.8
3.3
Power Management Signals
Symbol Type
Name and Function
LAN_
PWR_
I
GOOD
PME#
OD
AUX_PWR I
Power Good (Power-on Reset). The Power Good signal is used to indicate that stable
power is available for the 82540EP. When the signal is low, the 82540EP holds itself in
reset state and floats all PCI signals.
Power Management Event. The 82540EP device drives this signal low when it
receives a wake-up event and either the PME Enable bit in the Power Management
Control/Status Register or the Advanced Power Management Enable (APME) bit of the
Wake-up Control Register (WUC) is 1b.
Auxiliary Power. If the Auxiliary Power signal is high, then auxiliary power is available
and the 82540EP device should support the D3cold power state.
Impedance Compensation Signals
Symbol Type
Name and Function
ZN_COMP I/O
ZP_COMP I/O
N Device Impedance Compensation. This signal should be connected to an external
precision resistor (to VDD) that is indicative of the PCI trace load. This cell is used to
dynamically determine the drive strength required on the N-channel transistors in the
PCI I/O cells.
P Device Impedance Compensation. This signal should be connected to an external
precision resistor (to VSS) that is indicative of the PCI trace load. This cell is used to
dynamically determine the drive strength required on the P-channel transistors in the
PCI I/O cells.
SMB Signals
Symbol
SMBCLK
SMBDATA
SMB_
ALERT#
Type
Name and Function
I/O SMB Clock. The SMB Clock signal is an open drain signal for serial SMB interface.
I/O SMB Data. The SMB Data signal is an open drain signal for serial SMB interface.
O
SMB Alert. The SMB Alert signal is open drain for serial SMB interface.
EEPROM and Serial FLASH Interface Signals
Symbol
EEDI
EEDO
EECS
EESK
Type
Name and Function
O
EEPROM Data Input. The EEPROM Data Input pin is used for output to the memory
device.
I
EEPROM Data Output. The EEPROM Data Output pin is used for input from the
memory device. The EE_DO includes an internal pull-up resistor.
O
EEPROM Chip Select. The EEPROM Chip Select signal is used to enable the device.
O
EEPROM Serial Clock. The EEPROM Shift Clock provides the clock rate for the
EEPROM interface, which is approximately 1 MHz.
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