82540EP Datasheet, PDF (27/46 Pages) Intel Corporation – 82540EP Gigabit Ethernet Controller

Networking Silicon — 82540EP
Figure 2. PCI Clock Timing
3.3 V Clock
0.5 Vcc
0.4 Vcc
0.3 Vcc
Th
0.6 Vcc
Tcyc
0.2 Vcc
Tl
0.4 Vcc p-to-p
(minimum)
4.5.1.2
PCI Bus Interface Timing
Table 15. PCI Bus Interface Timing Parameters
Symbol
TVAL
TVAL(ptp)
TON
TOFF
TSU
TSU(ptp)
TH
TRRSU
TRRH
Parameter
PCI 66MHz
Min
Max
CLK to signal valid delay: bussed
signals
2
6
CLK to signal valid delay: point-
to-point signals
2
6
Float to active delay
2
Active to float delay
14
Input setup time to CLK: bussed
signals
3
Input setup time to CLK: point-to-
point signals
5
Input hold time from CLK
0
REQ64# to RST# setup time
10*TCYC
RST# to REQ64# hold time
0
PCI 33 MHz
Min
Max
2
11
2
12
2
28
7
10, 12
0
10*TCYC
0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Output timing measurements are as shown.
2. REQ# and GNT# signals are point-to-point and have different output valid delay and input setup times than
bussed signals. GNT# has a setup of 10 ns; REQ# has a setup of 12 ns. All other signals are bussed.
3. Input timing measurements are as shown.
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