82540EP Datasheet, PDF (17/46 Pages) Intel Corporation – 82540EP Gigabit Ethernet Controller

Networking Silicon — 82540EP
Symbol
FL_CE#
FL_SCK
FL_SI
FLSH_SO
Type
Name and Function
O
FLASH Chip Enable Output. Used to enable FLASH device.
O
FLASH Serial Clock Output. The clock rate of the serial FLASH interface is
approximately 1 MHz.
O
FLASH Serial Data Input. This pin is an output to the memory device.
FLASH Serial Data Output. This pin is an input from the FLASH memory.
Note: The 82540EP LAN-disable mechanism is implemented using this pin. It is
generally used when no Flash device is present (Flash disabled). If this pin is 1b (Vcc)
I
then the 82540EP is enabled. If the pin is 0b (Vss) then the 82540EP is disabled. This
signal should be sampled within 1s of the rising edge of LAN_PWR_GOOD and
PCI_RST_N. Note that this pin also has an internal pull-up that is sufficient enough to
enable the 82540EP if no Flash device is present.
Note: If the LAN-disable feature is used when a Flash device is present, then care must be taken by
system designers not to drive the FLSH_SO pin while the Flash device is driving it.
3.4
3.4.1
Miscellaneous Signals
LED Signals
3.4.2
Symbol
LINK_UP#
ACTIVITY#
LINK100#
LINK1000#
Type
Name and Function
O
LED0 / LINK Up. Programmable LED indication. Defaults to indicate link
connectivity.
O
LED1 / Activity. Programmable LED indication. Defaults to flash to indicate
transmit or receive activity.
O
LED2 / LINK 100. Programmable LED indication. Defaults to indicate link at
100 Mbps.
O
LED3 / LINK 1000. Programmable LED indication. Defaults to indicate link at
1000 Mbps.
Other Signals
Symbol
SDP[7:6]
SDP[1:0]
Type
Name and Function
Software Defined Pins. The Software Defined Pins are reserved and programmable
with respect to input and output capability. These default to input signals upon power-
TS ^{up but may be configured differently by the EEPROM. The upper four bits may be}
mapped to the General Purpose Interrupt bits if they are configured as input signals.
Note: SDP5 is not included in the group of Software Defined Pins.
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