82540EP Datasheet, PDF (26/46 Pages) Intel Corporation – 82540EP Gigabit Ethernet Controller

82540EP — Networking Silicon
Figure 1. AC Test Loads for General Output Pins
CL
4.5
Timing Specifications
Note: Timing specifications are subject to change. Verify with your local Intel sales office that you have
the latest information before finalizing a design.
4.5.1
4.5.1.1
PCI Bus Interface
PCI Bus Interface Clock
Table 14. PCI Bus Interface Clock Parameters
Symbol
Parameter^a
PCI 66 MHz
Min
Max
PCI 33 MHz
Min
Max
Units
TCYC
TH
TL
CLK cycle time
CLK high time
CLK low time
CLK slew rate
RST# slew rate^b
15
30
30
6
11
6
11
1.5
4
1
50
50
ns
ns
ns
4
V/ns
mV/ns
a. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the
minimum peak-to-peak portion of the clock waveform as shown.
b. The minimum RST# slew rate applies only to the rising (de-assertion) edge of the reset signal and ensures that system
noise cannot render a monotonic signal to appear bouncing in the switching range.
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