IA63484 Datasheet, PDF (5/32 Pages) InnovASIC, Inc – Advanced CRT Controller

IA63484
Advanced CRT Controller
Figure 2: ACRTC Block Diagram
res_n
Data Sheet
dreq_n
dack_n
done_n
irq_n
DMA
Control
Unit
Interrupt
Control
Unit
Register
Address
Data
20
Drawing
Processor ₁₆
draw_adrs[19:0]
draw_data[15:0]
draw_en
write
16
d[15:0]
cs_n
rs_n
rw_n
dtack_n
MPU
Interface
23 25
V _cc
V _SS
disp_adrs[19:0]
20
Display
Processor
15
raster_adrs[4:0]
chr_int
ccud
lpstb
2
Timing
Processor 2
gcud[1:0]
hsync
vsync
exsync
disp[1:0]
m_cyc
as
clk2
16
4
CRT
Interface
2
2
draw_n
mrd
mad[15:0]
ma19_16_ra[3:0]
ra4
chr
lpstb
cud1_n, cud2_n
hsync_n
vsync_n
exsync_n
disp1_n, disp2_n
mcyc
as_n
clk_2
ACRTC System Description:
Some CRT controllers provide a single bus interface to the frame buffer that must be shared with the host
MPU. However, refreshing large frame buffers, and accessing the frame buffer for drawing operations can
quickly saturate the shared bus.
The ACRTC uses separate host MPU and frame buffer interfaces. This allows the ACRTC full access to the
frame buffer for display refresh and drawing operations and minimizes the use of the MPU system bus by the
ACRTC. A related benefit is that a large frame buffer (2 MB for each ACRTC) can be used, even if the host
MPU has a smaller address space or segment size restriction.
The ACRTC can use an external Direct Memory Access Controller (DMAC) to increase system throughput
when many commands, parameters and data must be transferred to the ACRTC. Advanced DMAC features
such as the HD68450 “chaining” modes can be used to develop powerful graphics system architectures.
More cost-sensitive or less performance-sensitive applications might not require a DMAC. In these cases, the
interface to the ACRTC can be handled under MPU software control.
While both ACRTC bus interfaces (host MPU and frame buffer) are 16 bits wide, the ACRTC also offers an
8 bit MPU mode for easy connection to popular 8 bit busses.
Copyright © 2001
innovASIC
The End of Obsolescence™
ENG 21101041200
Page 5 of 32
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