IA63484 Datasheet, PDF (4/32 Pages) InnovASIC, Inc – Advanced CRT Controller

IA63484
Advanced CRT Controller
Data Sheet
I/O SIGNAL DESCRIPTION:
The diagram below describes the I/O characteristics for each signal on the IC. The signal names
correspond to the signal names on the pinout diagrams provided.
I/O Characteristics:
Signal Name I/O
res_n
I
d[15,0]
I/O
rw_n
I
cs_n
I
rs
I
dtack_n
O
irq_n
O
dreq_n
I
dack
I/O
done_n
I
clk_2
I/O
mad[15,0]
O
as_n
O
MA16^/R 0^-*
O
MA_{1 9}/ R A₃
RA₄
O
chr
O
mcyc
O
mrd
O
draw_n
O
disp1, disp2
O
cud1, cud2
vsync_n
O
hsync_n
exsync_n
I/O
lpstb
I
Group
MPU
Interface
DMAC
Interface
CRT
Interface
Description
ACRTC reset:
Data bus (three state): are the bidirectional data bus to the host mpu or dmac. D ₀ -D
are used in 8-bit data bus mode.
Read/write strobe: controls the direction of host/ACRTC transformers.
Chip Select: enables transfers between the host and the ACRTC.
Register Select: selects the ACRTC register to be accessed. It is usually connected to
the least significant bit of the host address bus.
Data transfer acknowledge (three state): output provides asynchronous bus cycle
timing. It is compatible with the HD68000 mpu dtack output.
Interrupt request (open drain): output generates interrupt service requests to the
host MPU.
DMA request: recieves DMA acknowledge timing from the host DMAC.
DMA acknoledge:
DMA done: terminates DMA transfer. It is compatible with the HD68450 DMAC
DONE signal.
ARTC clock: is the baasic operating clock, twice the frequency of the dot clock.
Multiplexed frame buffer address/data bus: are the multiplexed frame buffer
address/data bus.
Address strobe: output demultiplexes the address/data bus.
Higer-order address bits/character screen rastar address:MA16/R0- MA19/RA3 are
the upper bits of the graphics screen ddress multiplexed with th lower bits of the
character screen raster address.
Higer-order character screen rastar address bit: is the high bit of the character screen
raster address (up to 32 rasters.)
Graphic or character screen access: output indicates whether a graphic or character
screen is being accessed.
Frame buffer memory acess timing signal: is the frame buffer access timing output,
1/2 the frequency of clk_2.
Frame buffer memory read: output controls the frame buffer data bus direction.
Draw/refresh signal: output differentiates between drawing and CRT displayrefresh
cycles.
Display enable: programmable display enable outputs can enable, disable, and blanck
logical screens.
Coursor Display: outputs provides cursor timing programmed by ACRTC parameters
such as cursor definition, cursor mode, cursor address, etc.
CRT vertical sync pulse: outputs the crt vertical synchronization pulse.
CRT horizontal sync pulse: outputs the crt horizontal synchronization pulse.
External sync:allows synchronization between multiple ACRTSs and other videro
signal generators.
Lightpen strobe: is the lightpen input
Copyright © 2001
innovASIC
The End of Obsolescence™
ENG 21101041200
Page 4 of 32
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