IA63484 Datasheet, PDF (10/32 Pages) InnovASIC, Inc – Advanced CRT Controller

IA63484
Advanced CRT Controller
Data Sheet
Frame Buffer Interface:
The ACRTC allows for two types of independent frame memories. The first type is up to a 2 Mbyte
frame buffer and the second is a 128 Kbytes refresh memory. The chr output pin can access either
the Graphic or Character screen.
The width of the frame memory is defined by setting-up the memory width register (mwr) and
independently, the horizontal display width is defined by the horizontal display register (hdr). This
allows for the frame buffer area to be bigger than the display area; reference Figure 6.
Figure 6: Frame Memory and Display Screen Area
Start Address
Memory Width
Display Screen Area
text
Vertical
Display
Width
Horizontal Display Width
The ACRTC has two ways to access the frame memory (or buffer); (1) Display Memory Access
(three types) and (2) Graphic Address Increment mode.
Display Memory Access Modes:
In Single Access Mode, a display or drawing cycle is defined as two cycles of clk_2. During the first
cycle, the frame buffer display or drawing address is output. During the second clk_2 cycle, the
frame buffer data is read (display cycles and/or drawing cycles) or written (drawing cycles).
Display and drawing cycles contend for access to the frame buffer. The ACRTC allows the priority
to be defined as display priority or drawing priority. If display has priority, drawing cycles are only
allowed to occur during the horizontal or vertical fly back periods (a ‘flash less’ display is obtained).
If drawing has priority, drawing may occur during display (display may flash).
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