IA63484 Datasheet, PDF (15/32 Pages) InnovASIC, Inc – Advanced CRT Controller

IA63484
Advanced CRT Controller
Data Sheet
Hardware Access:
The ACRTC is connected to the host MPU as a standard memory-mapped peripheral that occupies
two word locations of the host’s address space. When rs=0, read operations access the status
register, and write operations access the address register.
The status register summarizes the ACRTC State; it monitors the overall state of the ACRTC for the
host MPU. When the MPU wants to access a direct access register, it puts the register’s address into
the ACRTC address register.
Direct Access:
The MPU accesses the direct access registers by loading the register address into the address register.
Then, when the MPU accesses the ACRTC with rs=1, the chosen register is accessed. The FIFO
entry register enables the MPU to access FIFO access registers using the ACRTC read and write
FIFOs.
The command control register controls overall ACRTC operations, such as aborting or pausing
commands, defining DMA protocols, and enabling/disabling interrupt sources.
The operation mode register defines basic parameters of ACRTC operation, such as frame buffer
access mode, display or drawing priority, cursor and display timing skew factors, and raster scan
mode.
The display control register independently enables and disables the four ACRTC logical address
screens (upper, base, lower, and window). It also contains 8 user-defined video attribute bits.
The timing control RAM registers define ACRTC timing, including timing specifications for CRT
control signals (hsync_n, vsync_n, etc.), logical display screen size and display period, and blink
period.
The display control RAM contains registers that define logical screen display parameters, such as start
address, raster address, and memory width. It also includes the cursor definition, zoom factor, and
lightpen registers.
FIFO Access:
For high-performance drawing, key drawing processor registers are coupled to the host MPU via the
ACRTC’s 16-byte read and write FIFOs. Figure and Figure illustrate the hardware and direct access
register information.
ACRTC commands are sent from the MPU via the write FIFO to the command register. As the
ACRTC completes a command, the next command is automatically fetched from the write FIFO and
put into the command register.
The pattern RAM defines drawing and painting patterns. It is accessed with the ACRTC’s Read
Pattern RAM (RPTN) and Write Pattern RAM (WPTN) register access commands.
The drawing parameter registers define detailed parameters of the drawing process, such as color
data, area control (hitting/clipping), and pattern RAM pointers. The drawing parameter registers are
accessed using the ACRTC’s Read Parameter Register (RPR) and Write Parameter Register (WPR)
commands. Figure illustrates the drawing parameter registers.
Copyright © 2001
innovASIC
The End of Obsolescence™
ENG 21101041200
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