IA63484 Datasheet, PDF (11/32 Pages) InnovASIC, Inc – Advanced CRT Controller

IA63484
Advanced CRT Controller
Data Sheet
In Interleaved Access Mode (dual access mode 0), display cycles and drawing cycles are interleaved.
A display or drawing cycle is defined as four cycles of clk_2.
• During the first clk_2 cycle, the ACRTC outputs the frame buffer display address.
• During the second clk_2 cycle, the display data is output from the frame buffer.
• During the third clk_2, the ACRTC outputs the frame buffer drawing address.
• During the fourth clk_2 cycle, the ACRTC reads or writes the drawing data.
In Superimposed Access Mode (dual access mode 1), two separate logical screens are accessed during
each display cycle. The display cycle is defined as four clk_2 cycles. If the third and fourth cycles are
not used for window display, they can be used for drawing; similar to the Interleaved Mode.
• During the first clk_2 cycle, the ACRTC outputs the background screen frame buffer address.
• During the second clk_2 cycle, the background screen displays data.
• During the third clk_2 cycle, the ACRTC outputs the window screen frame buffer address or the
drawing frame buffer address.
• During the fourth clk_2 cycle, the ACRTC reads (display or drawing) or writes (drawing) the
window screen display or drawing data.
Graphic Address Increment (GAI) Mode:
The ACRTC can be programmed to control the graphic display address in one of six ways, by
incrementing by 1, 2, 4, 8, and 16 words, 1 word every two display cycles, and no increment. Setting
GAI to increment by 2, 4, 8, or 16 words per display cycle achieves 2, 4, 8, or 16 times the video data
rate corresponding to GAI = 1. This allows the number of bits/logical pixel and logical pixel
resolution to be increased while meeting the clk_2 maximum frequency constraint.
When the frame buffer memory uses dynamic RAMs (DRAMs), the ACRTC automatically provides
DRAM refresh addressing.
During hsync_n low, the ACRTC outputs the values of an 8-bit DRAM refresh counter on the
multiplexed frame buffer address and data bus mad[15:0]. The counter is decremented on each
frame buffer access. The refresh address pin assignment (mad[15:0]) depends on the GAI mode.
The remaining mad and ma19_16_ra outputs not used for refresh addressing are cleared to a low
value.
Table 1: GAI and DRAM Refresh Addressing
Address Increment Mode
+1 (GAI = 000)
+2 (GAI = 001)
+4 (GAI = 010)
+8 (GAI = 011)
+16 (GAI = 100)
+0 (GAI = 101)
+1/2 (GAI = 11X)
Refresh Address Output Terminal
mad[7:0]
mad[8:1]
mad[9:2]
mad[10:3]
mad[11:4]
mad[7:0]
mad[7:0]
Copyright © 2001
innovASIC
The End of Obsolescence™
ENG 21101041200
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