IA63484 Datasheet, PDF (13/32 Pages) InnovASIC, Inc – Advanced CRT Controller

IA63484
Advanced CRT Controller
Data Sheet
Memory Map:
The ACTRC has over 200 bytes of accessible registers organized as Hardware, Direct, and FIFO
Access. Figure 8 illustrates the programming memory map model.
• The ACRTC registers are initialized by res_n as follows:
• Drawing and display operations are stopped
• Status register (SR) is initialized to $FF23
• Command control register (CCR) is initialized to $8000.
• Operation mode register bits MS and STR are reset to 0.
• All other registers are unaffected by res_n.
• The FIFO Entry (FE) pointer is cleared, and the written command/parameter and the read
data are lost.
• The DRAM refresh address is placed on the mad lines determined by graphic address
increment (GAI). Refresh continues to function until the start bit (STR) is set to 1. hsync_n
is also held low during the period from res_n until str is set by the MPU.
For directly accessible registers, the register address is shown as ‘rXX’, and FIFO accessible registers
are shown as ‘PrXX’, where XX is interpreted as an 8 bit hexadecimal value. Hexadecimal numbers
are denoted by a leading ‘$’.
Copyright © 2001
innovASIC
The End of Obsolescence™
ENG 21101041200
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