IA8044 Datasheet, PDF (40/49 Pages) InnovASIC, Inc – SDLC COMMUNICATIONS CONTROLLER

IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER
Data Sheet
A.C. Characteristics
TA = -40°C to +85°C, VDD = 5V ± 10%, VSS = 0V, Load Capacitance = 87pF
External Program Memory Characteristics
Symbol
Parameter
TLHLL
TAVLL
TLLAX
TLLIV
TLLPL
TPLPH
TPLIV
TPXIX
TPXIZ
TPXAV
TAVIV
TAZPL
TCY
ALE Pulse Width
Address Valid to ALE Low
Address Hold After ALE Low
ALE Low to Valid Instr. In.
ALE Low to PSENn Low
PSENn Pulse Width
PSENn Low to Valid Instr. In
Input Instr. Hold After PSENn
Input Instr. Float After PSENn
PSENn to Address Valid
Address to Valid Instr. In
Address Float to PSENn
Machine cycle
12 MHz Osc
Variable Clock 1/TCLCL
= 3.5 MHz TO 12 MHz Unit
Min
Max
Min
Max
171
2TCLCL+4
ns
75
TCLCL-8
ns
74
TCLCL-9
ns
298
4TCLCL-35 ns
83
TCLCL
ns
254
3TCLCL+4
ns
215
3TCLCL-35 ns
0
0
ns
76
TCLCL-7
ns
91
TCLCL+8
ns
373
5TCLCL-43 ns
-9
-9
ns
996
12TCLCL
ns
External Data Memory Characteristics
Symbol
Parameter
TRLRH
TWLWH
TLLAX
TRLDV
TRHDX
TRHDZ
TLLDV
TAVDV
TLLWL
TAVWL
TQVWX
TQVWH
TWHQX
TRLAZ
TWHLH
RDn Pulse Width
WRn Pulse Width
Address Hold After ALE
RDn Low to Valid Data In.
Data Hold After RDn
Data Float After RDn
ALE Low to Valid Data In
Address to Valid Data In.
ALE Low to RDn or WRn Low
Address to RDn or WRn Low
Data Valid to WRn Transistion
Data Setup Before WRn High
Data Held After WRn
RDn Low to Address Float
RDn or WRn High to ALE High
12 MHz Osc
Variable Clock 1/TCLCL =
3.5 MHz TO 12 MHz
Unit
Min Max
Min
Max
487
6TCLCL-13
ns
487
6TCLCL-13
ns
74
TCLCL-9
ns
383
5TCLCL-35 ns
0
0
ns
165
2TCLCL-2 ns
633
8TCLCL-34 ns
708
9TCLCL-42 ns
250
250 3TCLCL 3TCLCL
ns
325
4TCLCL-8
ns
76
TCLCL-7
ns
563
7TCLCL-20
ns
86
TCLCL+3
ns
9
9 ns
83
83 TCLCL TCLCL
ns
Copyright © 2003
innovASIC
The End of Obsolescence™
ENG210010112-00
Page 40 of 49
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