IA8044 Datasheet, PDF (22/49 Pages) InnovASIC, Inc – SDLC COMMUNICATIONS CONTROLLER

IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER
Data Sheet
General CPU Registers
Accumulator (ACC):
ACC is the Accumulator register. Most instructions use the accumulator to hold the
operand. The mnemonics for accumulator-specific instructions refer to accumulator as A, not
ACC.
ACC
Bit: 7
ACC.7
6
ACC.6
5
ACC.5
4
ACC.4
3
ACC.3
2
ACC.2
1
ACC.1
0
ACC.0
B register (B):
The B register is used during multiply and divide instructions. It can also be used as a
scratch-pad register to hold temporary data.
B
Bit: 7
B.7
6
B.6
5
B.5
4
B.4
3
B.3
2
B.2
1
B.1
0
B.0
Program Status Word (PSW):
Contains CPU status flags, register select bits and user flags.
PSW
Bit: 7
CY
6
AC
5
F0
4
RS1
3
RS0
2
OV
1
-
0
P
PSW.0
P
PSW.1
-
PSW.2
OV
PSW.3
RS0
PSW.4
RS1
PSW.5
F0
PSW.6
AC
PSW.7
CY
Parity flag, affected by hardware to indicate odd / even number
of “one” bits in the Accumulator, i.e. even parity.
User defined flag.
Overflow flag.
Register bank select control bit 0, used to select working
register bank.
Register bank select control bit 1, used to select working register
bank.
General purpose Flag 0 available for user.
Auxiliary Carry flag for carry out of or into bit 3.
Carry flag for carry out of or into bit 7.
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The End of Obsolescence™
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