IA8044 Datasheet, PDF (23/49 Pages) InnovASIC, Inc – SDLC COMMUNICATIONS CONTROLLER

IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER
The state of bits RS1, RS0 selects the working registers bank as follows:
RS1/0
00
01
10
11
Bank selected location
Bank 0 (00H – 07H)
Bank 1 (08H – 0FH)
Bank 2 (10H – 17H)
Bank 3 (18H – 1FH)
Data Sheet
Stack Pointer (SP):
The Stack Pointer is a 1-byte register initialized to 07H after reset. This register is incremented
before PUSH and CALL instructions, causing the stack to begin at location 08H. The stack pointer
points to a location in internal RAM.
SP
Bit: 7
SP.7
6
SP.6
5
SP.5
4
SP.4
3
SP.3
2
SP.2
1
SP.1
0
SP.0
Data Pointer (DPTR):
The Data Pointer (DPTR) is 2 bytes wide. The lower part is DPL, and the highest is DPH.
It can be loaded as 2 byte register (MOV DPTR,#data16) or as two registers (ea. MOV
DPL,#data8). It is generally used to access external code or data space (ea. MOVC
A,@A+DPTR or MOV A,@DPTR respectively).
DPH
Bit: 7
DPH.7
6
DPH.6
5
DPH.5
4
DPH.4
3
DPH.3
2
DPH.2
1
DPH.1
0
DPH.0
DPL
Bit: 7
DPL.7
6
DPL.6
5
DPL.5
4
DPL.4
3
DPL.3
2
DPL.2
1
DPL.1
0
DPL.0
Copyright © 2003
innovASIC
The End of Obsolescence™
ENG210010112-00
Page 23 of 49
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