IA8044 Datasheet, PDF (25/49 Pages) InnovASIC, Inc – SDLC COMMUNICATIONS CONTROLLER

IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER
Data Sheet
Interrupt Handling
The interrupt flags are sampled during each machine cycle. The samples are polled
during the next machine cycle. If an interrupt flag is captured, the interrupt system will
generate an LCALL instruction to the appropriate service routine, provided that this is not
disabled by the following conditions:
1. An interrupt of the same or higher priority is processed
2. The current machine cycle is not the last cycle of the instruction (the instruction can
not be interrupted).
3. The instruction in progress is RETI or any write to IE or IP registers.
Note that if an interrupt is disabled and the interrupt flag is cleared before the blocking
condition is removed, no interrupt will be generated, since the polling cycle will not sample
any active interrupt condition. In other words, the interrupt condition is not remembered.
Every polling cycle is new.
Interrupt Priority Register (IP):
This register sets the interrupt priority to high or low for each interrupt. When the bit is set it selects
high priority. Within each level the interrupts are prioritized as follows:
External interrupt 0
Timer/counter 0
External interrupt 1
Timer/counter 1
SIU.
An interrupt process routine cannot be interrupted by an interrupt of lesser or equal priority.
IP
Bit: 7
6
5
4
3
2
1
0
-
-
-
PS
PT1
PX1
PT0
PX0
IP.0
PX0
External Interrupt 0 interrupt priority bit.
IP.1
PT0
Timer 0. interrupt priority bit.
IP.2
PX1
External interrupt 1. interrupt priority bit.
IP.3
PT1
Timer 1 interrupt priority bit.
IP.4
PS
SIU interrupt priority bit.
IP.5
-
IP.6
-
IP.7
-
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The End of Obsolescence™
ENG210010112-00
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