IA8044 Datasheet, PDF (27/49 Pages) InnovASIC, Inc – SDLC COMMUNICATIONS CONTROLLER

IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER
Data Sheet
SIU – Serial Interface Unit
The SIU is a serial interface customized to support SDLC/HDLC protocol. As such it supports
Zero Bit insertion/deletion, flags automatic access recognition and a 16 bit CRC. The SIU has two
modes of operation AUTO and FLEXIBLE. The AUTO mode uses a subset of the SDLC
protocol implemented in hardware. This frees the CPU from having to respond to every frame but
limits the frame types. In the FLEXIBLE mode every frame is under CPU control and therefore
more options are available. The SIU is controlled by and communicates to the CPU by using
several special function registers (SFRs). Data transmitted by or received by the SIU is stored in the
192 byte internal RAM in blocks referred to as the transmit and receive buffers. The SIU can
support operation in one of three serial data link configurations: 1) half-duplex, point-to-point, 2)
half-duplex, multipoint, 3) loop mode.
SIU Special Function Registers
The CPU controls the SIU and receives status from the SIU via eleven special function registers.
The Serial Interface Unit Control Registers are detailed below:
Serial Mode Register (SMD):
The serial mode register sets the operational mode of the SIU. The CPU can read and write SMD.
The SIU can read SMD. To prevent conflicts between CPU and SIU accesses to SMD the CPU
should write SMD only when RTS and RBE bits in the STS register are both zero. SMD is normally
only accessed during initialization. This register is byte addressable.
SMD
Bit: 7
6
5
4
3
2
1
0
SCM2
SCM1
SCM0
NRZI
LOOP
PFS NB
NFCS
SMD.0
SMD.1
SMD.2
SMD.3
SMD.4
SMD.5
SMD.6
SMD.7
NFCS
NB
PFS
LOOP
NRZI
SCM0
SCM1
SCM2
When set selects No FCS field contained in the SDLC frame.
Non-buffered mode. No control field contained in SDLC frame.
Pre-frame sync mode. When set causes two bytes to be
transmitted before the first flag of the frame for DPLL
synchronization. If NRZI is set 00H is transmitted otherwise 55H.
This ensures that 16 transitions are sent before the opening flag.
When set selects loop configuration else point-to-point mode.
When set selects NRZI encoding otherwise NRZ.
Select clock mode - bit 0.
Select clock mode - bit 1.
Select clock mode - bit 2.
Copyright © 2003
innovASIC
The End of Obsolescence™
ENG210010112-00
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