IA8044 Datasheet, PDF (21/49 Pages) InnovASIC, Inc – SDLC COMMUNICATIONS CONTROLLER

IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER
Data Sheet
Reset
A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator
periods) while the oscillator is running. The CPU responds by generating an internal reset, which is
executed during the second cycle in which RST is high.
The internal reset sequence affects all SFRs as shown below. The internal reset sequence does not
affect the contents of internal RAM.
Reset Values
Register
PC
ACC
B
PSW
SP
DPTR
P0 – P3
IP
IE
TMOD
TCON
TH0
TL0
TH1
TL1
SMD
STS
NSNR
STAD
TBS
TBL
TCB
RBS
RBL
RFL
RCB
DMA CNT
FIFO1
FIFO2
FIFO3
SIUST
Reset value
0000H
00000000B
00000000B
00000000B
00000111B
0000H
11111111B
XXX00000B
0XX00000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
00000000B
00000000B
00000000B
00000000B
00000001B
Copyright © 2003
innovASIC
The End of Obsolescence™
ENG210010112-00
Page 21 of 49
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