IA8044 Datasheet, PDF (13/49 Pages) InnovASIC, Inc – SDLC COMMUNICATIONS CONTROLLER

IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER
Data Sheet
Ports
Ports P0, P1, P2 and P3 are Special Function Registers. The contents of the SFR can be observed on
corresponding pins on the chip. Writing a ‘1’ to any of the ports causes the corresponding pin to be
at high level (VCC), and writing a ‘0’ causes the corresponding pin to be held at low level (GND).
All four ports on the chip are bi-directional. Each of them consists of a Latch (SFR P0
to P3), an output driver, and an input buffer, so the CPU can output or read data through any
of these ports if they are not used for alternate purposes.
Ports P0, P1, P2 and P3 can perform some alternate functions. Ports P0 and P2 are
used to access external memory. In this case, port ‘p0’ outputs the multiplexed lower 8 bits of
address with ‘ale’ strobe high and then reads/writes 8 bits of data. Port P2 outputs the higher 8
bits of address. Keeping ‘ea’ pin low (tied to GND) activates this alternate function for ports
P0 and P2.
Port P3 and P1 can perform some alternate functions. The pins of Port P3 are multifunctional.
They can perform additional functions as described below.
Pin Symbol
P3.0 RxD, I/O
Function
In point-to-point or multipoint configurations (SMD.3 = 0) this pin
is I/O and signals the direction of data flow on DATA (P3.1). In loop mode
(SMD.3 = 1) and diagnostic mode this pin is RxD, Receive Data
input.
P3.1 TxD, DATA In point to point or multipoint configurations (SMD.3 = 0) this pin
is DATA and is the transmit/receive data pin. In loop mode
(SMD.3 = 1) this pin is the transmit data, TxD, pin. Writing a ‘0’ to
this port buffer bit enables the diagnostic mode.
P3.2 INT0
External interrupt 0 input. Also gate control input for counter 0.
P3.3 INT1
External interrupt 1 input. Also gate control input for counter 1.
P3.4 T0
Timer/Counter 0 external input. Setting the appropriate bits in the
Special Function Registers TCON and TMOD activates this
function.
P3.5 T1, SCLK
Timer/Counter 1 external input. Setting the appropriate bits in the
Special Function Registers TCON and TMOD activates this
function. . Can also function as the external clock source for the SIU.
P3.6 WR
External Data Memory write strobe, active LOW. This function
is activated by a CPU write access to External Data Memory
(i.e. MOVX @DPTR, A).
Copyright © 2003
innovASIC
The End of Obsolescence™
ENG210010112-00
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