TC1784 Datasheet, PDF (98/123 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1784
Electrical ParametersAC Parameters
5.3.6 JTAG Interface Timing
The following parameters are applicable for communication through the JTAG debug
interface. The JTAG module is fully compliant with IEEE1149.1-2000.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Table 27
JTAG Interface Timing Parameters
(Operating Conditions apply)
Parameter
Symbol
Values
Min. Typ. Max.
TCK clock period
TCK high time
TCK low time
TCK clock rise time
TCK clock fall time
TDI/TMS setup
to TCK rising edge
t₁ SR 25
–
–
t₂ SR 10
–
–
t₃ SR 10
–
–
t₄ SR –
–
4
t₅ SR –
–
4
t₆ SR 6
–
–
TDI/TMS hold
t₇ SR 6
–
–
after TCK rising edge
TDO valid after TCK falling t₈ CC –
–
13
edge¹⁾ (propagation delay) _{t8 CC 3}
–
–
TDO hold after TCK falling t₁₈ CC 2
–
–
edge¹⁾
TDO high imped. to valid t₉ CC –
–
14
from TCK falling edge¹⁾²⁾
TDO valid to high imped. t₁₀ CC –
–
13.5
from TCK falling edge¹⁾
1) The falling edge on TCK is used to generate the TDO timing.
2) The setup time for TDO is given implicitly by the TCK cycle time.
Unit Note /
Test Condition
ns –
ns –
ns –
ns –
ns –
ns –
ns –
ns C_L = 50 pF
ns C_L = 20 pF
ns
ns C_L = 50 pF
ns C_L = 50 pF
Data Sheet
91
V 1.1.1, 2014-05