TC1784 Datasheet, PDF (96/123 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1784
Electrical ParametersAC Parameters
accumulated jitter remains at a constant value. Further, a lower LMB-Bus clock
frequency f_LMB results in a higher absolute maximum jitter value.
Note: The specified PLL jitter values are valid if the capacitive load per pin does not
exceed C_L = 20 pF with the maximum driver and sharp edge.
Note: The maximum peak-to-peak noise on the pad supply voltage, measured between
V_DDOSC3 and V_SSOSC, is limited to a peak-to-peak voltage of V_PP = 100 mV for noise
frequencies below 300 KHz and V_PP = 40 mV for noise frequencies above
300 KHz.
The maximum peak-to peak noise on the pad supply voltage, measured between
V_DDOSC and V_SSOSC, is limited to a peak-to-peak voltage of V_PP = 100 mV for noise
frequencies below 300 KHz and V_PP = 40 mV for noise frequencies above
300 KHz.
These conditions can be achieved by appropriate blocking of the supply voltage
as near as possible to the supply pins and using PCB supply and ground planes.
Oscillator Watchdog (OSC_WDT)
The expected input frequency is selected via the bit field SCU_OSCCON.OSCVAL. The
OSC_WDT checks for too low frequencies and for too high frequencies.
The frequency that is monitored is f_OSCREF which is derived for f_OSC.
(8)
f
f
= ----------------^O--^S---^C-------------
OSCREF _{OSCVAL + 1}
The divider value SCU_OSCCON.OSCVAL has to be selected in a way that f_OSCREF is
2.5 MHz.
Note: f_OSCREF has to be within the range of 2 MHz to 3 MHz and should be as close as
possible to 2.5 MHz.
The monitored frequency is too low if it is below 1.25 MHz and too high if it is above
7.5 MHz. This leads to the following two conditions:
• Too low: f_OSC < 1.25 MHz × (SCU_OSCCON.OSCVAL+1)
• Too high: f_OSC > 7.5 MHz × (SCU_OSCCON.OSCVAL+1)
Note: The accuracy is 30% for these boundaries.
Data Sheet
89
V 1.1.1, 2014-05