TC1784 Datasheet, PDF (95/123 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1784
5.3.4
Phase Locked Loop (PLL)
Electrical ParametersAC Parameters
Table 25 PLL_SysClk Parameters
Parameter
Symbol
Min.
Accumulated Jitter
PLL base frequency
D_P CC -7
f_PLLBASE 50
CC
VCO input frequency
VCO frequency range
PLL lock-in time
f_REF CC 8
f_VCO CC 400
t_L CC 14
14
Values
Typ. Max.
−
7
200 320
Unit Note /
Test Condition
ns
MHz
−
16
MHz
−
720 MHz
−
200 μs N > 32
−
400 μs N ≤ 32
Phase Locked Loop Operation
When PLL operation is enabled and configured, the PLL clock f_VCO (and with it the LMB-
Bus clock f_LMB) is constantly adjusted to the selected frequency. The PLL is constantly
adjusting its output frequency to correspond to the input frequency (from crystal or clock
source), resulting in an accumulated jitter that is limited. This means that the relative
deviation for periods of more than one clock cycle is lower than for a single clock cycle.
This is especially important for bus cycles using wait states and for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is negligible.
Two formulas are defined for the (absolute) approximate maximum value of jitter D_m in
[ns] dependent on the K2 - factor, the LMB clock frequency f_LMB in [MHz], and the
number m of consecutive f_LMB clock periods.
for
(K2 ≤ 100)
and
(m ≤ (f_LMB[MHz]) ⁄ 2)
Dm[ns]
=
⎛
⎝
-------------------7---4---0-------------------
K2 × f_LMB[MHz]
+
5_⎠⎞
×
⎛
⎝
-⁽--1----–-----0---^,---0---1----^×-----K-----2---⁾----^×-----⁽--m------–-----1----⁾
0, 5 × f_LMB[MHz] – 1
+
0,
01
×
K2_⎠⎞
(6)
else
Dm[ns] = -------------------7---4---0------------------- + 5
(7)
K2 × f_LMB[MHz]
With rising number m of clock cycles the maximum jitter increases linearly up to a value
of m that is defined by the K2-factor of the PLL. Beyond this value of m the maximum
Data Sheet
88
V 1.1.1, 2014-05