TC1784 Datasheet, PDF (106/123 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1784
5.3.8.3
Electrical ParametersAC Parameters
SSC Master/Slave Mode Timing
The SSC parameters are vaild for C_L = 50 pF and strong driver medium edge.
Table 32 SSC Parameters
Parameter
SCLK clock period¹⁾²⁾³⁾
MTSR/SLSOx delay form
SCLK rising edge
Symbol
Min.
t₅₀ CC
t₅₁ CC
2x1/
f_FPI
0
Values
Typ. Max.
−
−
−
8
Unit Note /
Test Condition
ns
ns
MRST setup to SCLK
t₅₂ SR 16.5 −
−
ns
latching edge³⁾
MRST hold from SCLK t₅₃ SR 0
−
−
ns
latching edge³⁾
SCLK input clock
period¹⁾³⁾
SCLK input clock duty
cycle
t₅₄ SR
t₅₅_t₅₄
SR
4x1/ −
f_FPI
45
−
−
ns
55
%
MTSR setup to SCLK
t₅₆ SR 1 / f_FPI −
−
ns
latching edge³⁾⁴⁾
MTSR hold from SCLK t₅₇ SR 1 / f_FPI −
−
ns
latching edge
+5
SLSI setup to first SCLK t₅₈ SR 1 / f_FPI −
−
ns
latching edge
+5
SLSI hold from last SCLK t₅₉ SR 7
−
−
ns
latching edge ⁵⁾
MRST delay from SCLK t₆₀ CC 0
−
16.5 ns
shift edge
SLSI to valid data on
t₆₁ CC −
−
16.5 ns
MRST
1) SCLK signal rise/fall times are the same as the rise/fall times of the pad.
2) SCLK signal high and low times can be minimum 1xTSSC.
3) TSSCmin = TSYS = 1/fSYS.
4) Fractional divider switched off, SSC internal baud rate generation used.
5) For CON.PH=1 slave select must not be removed before the following shifting edge. This mean, that what ever
is configured (shifting / latching first), SLSI must not be de-actived before the last trailing edge from the pair
of shifting / latching edges.
Data Sheet
99
V 1.1.1, 2014-05