XC2786X Datasheet, PDF (91/120 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance

XC2786X
XC2000 Family Derivatives
Electrical Parameters
4.5
Flash Memory Parameters
The XC2786X is delivered with all Flash sectors erased and with no protection installed.
The data retention time of the XC2786X’s Flash memory (i.e. the time after which stored
data can still be retrieved) depends on the number of times the Flash memory has been
erased and programmed.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Table 23
Flash Characteristics
(Operating Conditions apply)
Parameter
Programming time per
128-byte page
Erase time per
sector/page
Symbol
Limit Values
Min. Typ. Max.
t_PR
–
3¹⁾
3.5
Unit
ms
Note / Test
Condition
ms
t_ER
–
4¹⁾
5
ms ms
Data retention time
t_RET
20
–
–
years 1,000 erase /
program
cycles
Flash erase endurance for N_ER
15,000 –
–
cycles Data retention
user sectors²⁾
time 5 years
Flash erase endurance for N_SEC 10
–
–
cycles Data retention
security pages
time 20 years
Drain disturb limit
N_DD
64
–
–
cycles ³⁾
1) Programming and erase times depend on the internal Flash clock source. The control state machine needs a
few system clock cycles. This requirement is only relevant for extremely low system frequencies.
In the XC2786X erased areas must be programmed completely (with actual code/data or dummy values)
before that area is read.
2) A maximum of 64 Flash sectors can be cycled 15,000 times. For all other sectors the limit is 1,000 cycles.
3) This parameter limits the number of subsequent programming operations within a physical sector. The drain
disturb limit is applicable if wordline erase is used repeatedly. For normal sector erase/program cycles this
limit will not be violated.
Access to the XC2786X Flash modules is controlled by the IMB. Built-in prefetch
mechanisms optimize the performance for sequential access.
Flash access waitstates only affect non-sequential access. Due to prefetch
mechanisms, the performance for sequential access (depending on the software
structure) is only partially influenced by waitstates.
Data Sheet
89
V2.1, 2008-08