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XC2786X Datasheet, PDF (35/120 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance
XC2786X
XC2000 Family Derivatives
General Device Information
Table 4
Pin Definitions and Functions (cont’d)
Pin Symbol
Ctrl. Type Function
2,
36,
38,
72,
74,
108,
110,
144
VDDPB
-
PS/B Digital Pad Supply Voltage for Domain B
Connect decoupling capacitors to adjacent
VDDP/VSS pin pairs as close as possible to the pins.
Note: The on-chip voltage regulators and all ports
except P5, P6, and P15 are fed from supply
voltage VDDPB.
1, VSS
37,
73,
109
-
PS/-- Digital Ground
All VSS pins must be connected to the ground-line
or ground-plane.
Note: Also the exposed pad is connected to VSS.
The respective board area must be
connected to ground (if soldered) or left free.
1) To generate the reference clock output for bus timing measurement, fSYS must be selected as source for
EXTCLK and P2.8 must be selected as output pin. Also the high-speed clock pad must be enabled. This
configuration is referred to as reference clock output signal CLKOUT.
2) Pin TRef was used to control the core voltage generation in step AA. For that step, pin TRef must be connected
to VDDPB.
This connection is no more required from step AB on. For the current step, pin TRef is logically not connected.
Future derivatives will feature an additional general purpose IO pin at this position.
Data Sheet
33
V2.1, 2008-08