XC2786X Datasheet, PDF (104/120 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance

XC2786X
XC2000 Family Derivatives
Electrical Parameters
Table 30
External Bus Cycle Timing for Lower Voltage Range
(Operating Conditions apply)
Parameter
Symbol
Limits
Unit Note
Min. Typ. Max.
Output valid delay for:
RD, WR(L/H)
t₁₀ CC –
20
ns
Output valid delay for:
BHE, ALE
t₁₁ CC –
20
ns
Output valid delay for:
t₁₂ CC –
A23 … A16, A15 … A0 (on P0/P1)
22
ns
Output valid delay for:
A15 … A0 (on P2/P10)
t₁₃ CC –
22
ns
Output valid delay for:
CS
t₁₄ CC –
20
ns
Output valid delay for:
t₁₅ CC –
D15 … D0 (write data, MUX-mode)
21
ns
Output valid delay for:
D15 … D0 (write data, DEMUX-
mode)
t₁₆ CC –
21
ns
Output hold time for:
RD, WR(L/H)
t₂₀ CC 0
10
ns
Output hold time for:
BHE, ALE
t₂₁ CC 0
10
ns
Output hold time for:
t₂₃ CC 0
A23 … A16, A15 … A0 (on P2/P10)
10
ns
Output hold time for:
CS
t₂₄ CC 0
10
ns
Output hold time for:
D15 … D0 (write data)
t₂₅ CC 0
10
ns
Input setup time for:
READY, D15 … D0 (read data)
t₃₀ SR 29
–
ns
Input hold time for:
READY, D15 … D0 (read data)¹⁾
t₃₁ SR -6
–
ns
1) Read data are latched with the same internal clock edge that triggers the address change and the rising edge
of RD. Address changes before the end of RD have no impact on (demultiplexed) read cycles. Read data can
change after the rising edge of RD.
Data Sheet
102
V2.1, 2008-08