TLE6262G Datasheet, PDF (9/38 Pages) Infineon Technologies AG – Fault Tolerant CAN - LDO

Final Data TLE 6262 G
SPI (serial peripheral interface)
The 16-bit wide programming word or input word (see table 1) is read in via the data input
DI, and this is synchronized with the clock input CLK supplied by the µC. The diagnosis
word appears synchronously at the data output DO (see table 3).
The transmission cycle begins when the chip is selected by the chip select not input CSN
(H to L). After the CSN input returns from L to H, the word that has been read in becomes
the new control word. The DO output switches to tristate status at this point.
For details of the SPI timing please refer to figure 3 to 7.
Oscillator
All internal delay times are referring to the internal oscillator frequency, which is set by
an external resistor from pin OSC to GND. The oscillator frequency and the resulting
internal cycling time can be calculated by the equations:
f_OSC
=
2_---8_---,_---4_--5_---´_---1_---0_---⁹_--[_---H_----z_---W_------]
R_OSC
t_CYL
=
----³---²----
f_OSC
Window Watchdog, Reset and 3V-Supervisor
When the output voltage V_CC exceeds the reset threshold voltage V_RT the reset output
RO is switched HIGH after a delay time of 16 cycles. This is necessary for a defined start
of the microcontroller when the application is switched on. As soon as an under-voltage
condition of the output voltage (V_CC < V_RT) appears, the reset output RO is switched
LOW again. The LOW signal is guaranteed down to an output voltage V_CC ³ 1V. Please
refer to fig.11, reset timing diagram.
Should the output voltage fall short of the 3V-supervisor threshold V_ST an internal flip-
flop is set LOW. The SPI diagnosis bit 7 monitors this. In normal operation this flip-flop
has to be activated via the SPI input bit 7. This feature is useful e.g. to monitor that the
RAM data of the microcontroller might be damaged or the application is connected to V_S
the first time.
After the above described delayed reset (LOW to HIGH transition of RO) the window
watchdog circuit is started by opening a long open window of 32 cycles. Now the
microcontroller has to service a watchdog trigger signal via the SPI interface (input bit 0).
A watchdog trigger is detected as a falling edge by sampling for 2 cycles a HIGH followed
by 2 cycles LOW of the SPI input bit 0. The long open window ensures a simple and fast
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version: 2.03 date: 2002-03-20