TLE6262G Datasheet, PDF (10/38 Pages) Infineon Technologies AG – Fault Tolerant CAN - LDO

Final Data TLE 6262 G
synchronization of the TLE 6262 watchdog timing to the watchdog services of the
microcontroller.
After the first trigger the watchdog has to be serviced by meeting an open window of 20
cycles that follows a closed window of 12 cycles. A correct watchdog service
immediately results in starting the next closed window. Please refer to fig. 10, watchdog
timing diagram.
If the trigger signal does not meet the open window (trigger to early or to late) the reset
output RO is set LOW for a period of 4 cycles. Afterwards a long open window is started
again. In addition, the SPI diagnosis bit 2 is set HIGH to monitor a watchdog reset.
Both, the undervoltage reset and the watchdog reset are setting all SPI input bits LOW.
To avoid a cyclic wake-up of the microcontroller in low power mode (sleep mode) the
watchdog circuit can be automatically disabled at low output currents (I_CC < I_CCWD). To
activate this feature the SPI input bit 8 has to be set HIGH. In this under-current mode
the low side switches are switched off automatically by the TLE 6262 to guarantee fail-
save operation of the application. When the microcontroller returns back to normal mode
(I_CC > I_CCWD) the first closed window is transformed to an open window so that the total
open window time is 32 cycles. This ensures a more simple and fast synchronization of
the TLE 6262 watchdog timing to the watchdog services of the microcontroller.
Flash program mode
To disable the watchdog feature a flash program mode is available. This mode is
selected by applying a voltage of 6.8V < V_PWM < 7.2V at pin PWM. This is useful e.g. if
the flash-memory of the micro has to be programmed and therefore a regular watchdog
triggering is not possible. If the SPI is required in the flash program mode to change e.g.
the mode of the TLE6262 the first input telegram has to be “00000000”.
High Side Switch 1
The high side output OUTH1 is able to switch loads up to 250 mA. Its on-resistance is
1.0 W typ. @ 25°C. This switch can be controlled either via the PWM input or the SPI
input bit 1. When the input PWM is used it has to be enabled by setting the SPI input bit
11 HIGH. In case of both control inputs being active the PWM signal is masked by the
SPI signal (see fig. 8, High Side Switch 1 Timing Diagram).
The SPI diagnosis bit 14 monitors a thermal shutdown of the switches, whereas bit 0
flags a thermal prewarning. By this the microcontroller is able to reduce the power
dissipation of the TLE 6262 by switching off functions of minor priority before the
temperature threshold of the thermal shutdown is reached. Further OUTH1 is protected
against short circuit and overload. The SPI diagnosis bit 1 indicates an overload of
OUTH1. As soon as the under-voltage condition of the supply voltage is met (V_S <
V_UVOFF), the switches are automatically disabled by the under-voltage lockout circuit.
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version: 2.03 date: 2002-03-20