TLE6262G Datasheet, PDF (30/38 Pages) Infineon Technologies AG – Fault Tolerant CAN - LDO

3
Timing Diagrams
Final Data TLE 6262 G
CSN
CLK
DI
DO
eg.
HS1
CSN High to Low & rising edge of CLK: DO is enabled. Status information is transfered to Output Shift Register
CSN Low to High: Data from Shift-Register is transfered to Output Power Switches
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
actual Data
_
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DI: Data will be accepted on the falling edge of CLK-Signal
previous Status
0_ _1 _2 _3 4_ 5_ _6 _7 _8 _9 1_0 1_1 1_2 1_3 1_4 1_5
DO: State will change on the rising edge of CLK-Signal
old Data
time
01
new Data
+0 ¹⁺
actual Status
01
actual Data
Figure 4
Data Transfer Timing
30
version: 2.03 date: 2002-03-20