TLE6262G Datasheet, PDF (3/38 Pages) Infineon Technologies AG – Fault Tolerant CAN - LDO

Final Data TLE 6262 G
1.3 Pin Definitions and Functions
Pin No. Symbol Function
1
CANH CAN-H bus line; HIGH in dominant state
2
RTH
Termination input for CANH
3
RO
Reset output; open drain output; integrated pull up; active low
4
CANL CAN-L bus line; LOW in dominant state
5
RTL
Termination input for CANL
6, 7, 8, 9, GND
20, 21,
22, 23
Ground; to reduce thermal resistance place cooling areas on
PCB close to this pins.
10
OUTH1 High side output 1; controlled via PWM input and/or SPI input,
short circuit protected
11
OUTL1 Low side output 1; SPI controlled, with active zener
12
OUTL2 Low side output 2; SPI controlled, with active zener
13
OUTH2 High side output 2; SPI controlled
14
OUTH3 High side output 3; SPI controlled, in low power mode controlled
by internal autotiming function if selected
15
VS
Power supply; block to GND directly at the IC with ceramic
capacitor
16
CSN
SPI interface chip select not; CSN is an active low input; serial
communication is enabled by pulling the CSN terminal low; CSN
input should only be transitioned when CLK is low; CSN has an
internal active pull up and requires CMOS logic level inputs
17
DO
SPI interface data out; this tristate output transfers diagnosis
data to the control device; the output will remain 3-stated unless
the device is selected by a low on Chip-Select-Not (CSN); see
table 3 for diagnosis protocol
18
DI
SPI interface data in; receives serial data from the control
device; serial data transmitted to DI is a 16 bit control word with
the Least Significant Bit (LSB) being transferred first: the input
has an active pull down and requires CMOS logic level inputs; DI
will accept data on the falling edge of CLK-signal; see table 2 for
input data protocol
19
CLK
SPI interface clock input; clocks the shiftregister; CLK has an
internal active pull down and requires CMOS logic level inputs
3
version: 2.03 date: 2002-03-20