TC1767 Datasheet, PDF (86/126 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1767
Electrical Parameters
Table 9
Operating Condition Parameters
Parameter
Symbol
Values
Unit Note /
Min. Typ. Max.
Test Condition
Absolute sum of short Σ|I_{SC_PG}| –
circuit currents of a pin
SR
group (see Table 10)
– 20 mA See note
Inactive device pin
current
Absolute sum of short
circuit currents of the
device
I_ID
SR -1
Σ|I_{SC_D}|
–
SR
–1
mA All power supply
voltages V_DDx = 0
– 100 mA See note⁴⁾
External load
capacitance
C_L
SR –
––
pF Depending on pin
class. See DC
characteristics
1) Digital supply voltages applied to the TC1767 must be static regulated voltages which allow a typical voltage
swing of ±5%.
2) Voltage overshoot up to 1.7 V is permissible at Power-Up and PORST low, provided the pulse duration is less
than 100 µs and the cumulated summary of the pulses does not exceed 1 h.
3) Voltage overshoot up to 4 V is permissible at Power-Up and PORST low, provided the pulse duration is less
than 100 µs and the cumulated summary of the pulses does not exceed 1 h.
4) See additional document “TC1767 Pin Reliability in Overload“ for definition of overload current on digital pins.
5) The overload coupling factor (kA) defines the worst case relation of an overload condition (IOV) at one pin to
the resulting leakage current (IleakTOT) into an adjacent pin: IleakTOT = ±kA × |IOV| + IOZ1.
Thus under overload conditions an additional error leakage voltage (VAEL) will be induced onto an adjacent
analog input pin due to the resistance of the analog input source (RAIN). That means VAEL = RAIN ×
|IleakTOT|.
The definition of adjacent pins is related to their order on the silicon.
The Injected leakage current always flows in the opposite direction from the causing overload current.
Therefore, the total leakage current must be calculated as an algebraic sum of the both component leakage
currents (the own leakage current IOZ1 and the optional injected leakage current).
6) The PLL jitter characteristics add to this value according to the application settings. See the PLL jitter
parameters.
7) Applicable for digital outputs.
Table 10 Pin Groups for Overload/Short-Circuit Current Sum Parameter
Group Pins
1
P5.[14:8]
2
P1.[14:12]; P2.[7:0]
3
P4.[3:0]
4
P1.[3:2]; P1.[11:8]
Data Sheet
82
V1.3, 2009-09