TC1767 Datasheet, PDF (30/126 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1767
Introduction
normally written to Flash by the CPU, but may also be issued by the DMA controller (or
OCDS).
The Flash also features an advanced read/write protection architecture, including a read
protection for the whole Flash array (optionally without Data Flash) and separate write
protection for all sectors (only Program Flash). Write protected sectors can be made re-
programmable (enabled with passwords), or they can be locked for ever (ROM function).
Each sector can be assigned to up to three different users for write protection. The
different users are organized hierarchically.
Program Flash Features and Functions
• 2 Mbyte on-chip Program Flash in PMU0.
• Any use for instruction code or constant data.
• 256 bit read interface (burst transfer operation).
• Dynamic correction of single-bit errors during read access.
• Transfer rate in burst mode: One 64-bit double-word per clock cycle.
• Sector architecture:
– Eight 16 Kbyte, one 128 Kbyte and seven 256 Kbyte sectors.
– Each sector separately erasable.
– Each sector lockable for protection against erase and program (write protection).
• One additional configuration sector (not accessible to the user).
• Optional read protection for whole Flash, with sophisticated read access supervision.
Combined with whole Flash write protection — thus supporting protection against
Trojan horse programs.
• Sector specific write protection with support of re-programmability or locked forever.
• Comfortable password checking for temporary disable of write or read protection.
• User controlled configuration blocks (UCB) in configuration sector for keywords and
for sector-specific lock bits (one block for every user; up to three users).
• Pad supply voltage (V_DDP) also used for program and erase (no VPP pin).
• Efficient 256 byte page program operation.
• All Flash operations controlled by CPU per command sequences (unlock sequences)
for protection against unintended operation.
• End-of-busy as well as error reporting with interrupt and bus error trap.
• Write state machine for automatic program and erase, including verification of
operation quality.
• Support of margin check.
• Delivery in erased state (read all zeros).
• Global and sector status information.
• Overlay support with SRAM for calibration applications.
• Configurable wait state selection for different CPU frequencies.
• Endurance = 1000; minimum 1000 program/erase cycles per physical sector;
reduced endurance of 100 per 16 KB sector.
• Operating lifetime (incl. Retention): 20 years with endurance=1000.
Data Sheet
26
V1.3, 2009-09