TC1767 Datasheet, PDF (120/126 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1767
5.3.8.3 SSC Master / Slave Mode Timing
Electrical Parameters
Table 25
Parameter
SSC Master/Slave Mode Timing
(Operating Conditions apply), C_L = 50 pF
Symbol
Values
Min.
Typ. Max.
Master Mode Timing
SCLK clock period
t₅₀ CC 2 × T_SSC –
–
MTSR/SLSOx delay from t₅₁ CC 0
SCLK rising edge
–8
MRST setup to SCLK
falling edge
t₅₂ SR 13
––
MRST hold from SCLK
falling edge
t₅₃ SR 0
––
Slave Mode Timing
SCLK clock period
SCLK duty cycle
MTSR setup to SCLK
latching edge
t₅₄ SR 4 × T_SSC –
–
t₅₅/t₅₄ SR 45
– 55
t₅₆ SR T_SSC + 5 –
–
MTSR hold from SCLK
latching edge
t₅₇ SR T_SSC + 5 –
–
SLSI setup to first SCLK t₅₈ SR T_SSC + 5 –
–
latching edge
SLSI hold from last SCLK t₅₉ SR 7
latching edge
––
MRST delay from SCLK
shift edge
t₆₀ CC 0
– 15
SLSI to valid data on MRST t₆₁ CC –
– 10
1) SCLK signal rise/fall times are the same as the A2 Pads rise/fall times.
2) SCLK signal high and low times can be minimum 1 × T_SSC.
3) T_SSCmin = T_SYS = 1/f_SYS. When f_SYS = 80 MHz, t₅₀ = 25 ns.
4) Fractional divider switched off, SSC internal baud rate generation used.
Unit Note /
Test Con
dition
ns ¹⁾²⁾³⁾
ns –
ns ³⁾
ns ³⁾
ns ¹⁾³⁾
%–
ns ³⁾⁴⁾
ns ³⁾⁴⁾
ns ³⁾
ns –
ns –
ns –
Data Sheet
116
V1.3, 2009-09