TC1767 Datasheet, PDF (110/126 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1767
5.3.5 Phase Locked Loop (PLL)
Electrical Parameters
Note: All PLL characteristics defined on this and the next page are not subject to
production test, but verified by design characterization.
Table 20 PLL Parameters (Operating Conditions apply)
Parameter
Symbol
Min.
Values
Typ. Max.
Unit Note /
Test Con
dition
Accumulated jitter
|D_m|
–
–
7
ns –
VCO frequency range
f_VCO
400
–
800
MHz –
VCO input frequency range f_REF
8
–
16
MHz –
PLL base frequency¹⁾
f_PLLBASE 50
200 320
MHz –
PLL lock-in time
t_L
–
–
200
µs –
1) The CPU base frequency with which the application software starts after PORST is calculated by dividing the
limit values by 16 (this is the K2 factor after reset).
Phase Locked Loop Operation
When PLL operation is enabled and configured, the PLL clock f_VCO (and with it the LMB-
Bus clock f_LMB) is constantly adjusted to the selected frequency. The PLL is constantly
adjusting its output frequency to correspond to the input frequency (from crystal or clock
source), resulting in an accumulated jitter that is limited. This means that the relative
deviation for periods of more than one clock cycle is lower than for a single clock cycle.
This is especially important for bus cycles using waitstates and for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is negligible.
Two formulas are defined for the (absolute) approximate maximum value of jitter D_m in
[ns] dependent on the K2 - factor, the LMB clock frequency f_LMB in [MHz], and the
number m of consecutive f_LMB clock periods.
for
(K2 ≤ 100)
and
(m ≤ (f_LMB[MHz]) ⁄ 2)
Dm[ns]
=


-------------------7---4---0-------------------
K2 × f_LMB[MHz]
+
5_
×


-⁽--1----–-----0---^,---0---1----^×-----K-----2---⁾----^×-----⁽--m------–-----1----⁾
0, 5 × f_LMB[MHz] – 1
+
0,
01
×
K
2_
(2)
else
Dm[ns] = -------------------7---4---0------------------- + 5
(3)
K2 × f_LMB[MHz]
Data Sheet
106
V1.3, 2009-09