HYS72D256520GR Datasheet, PDF (8/25 Pages) Infineon Technologies AG – 184 Pin Registered Double Data Rate SDRAM Modules

2
Pin Configuration
HYS72D256520GR-7-A
Registered Double Data Rate SDRAM Modules
Pin Configuration
Table 3 Pin Definitions and Functions
Symbol
Type
A0 - A11,A12
BA0, BA1
DQ0 - DQ63
CB0 - CB7
RAS
CAS
WE
CKE0, CKE1
DQS0 - DQS8
CK0, CK0
DQS9 - DQS17
CS0 - CS1
V_DD
V_SS
V_DDQ
V_DDID
V_DDSPD
V_REF
SCL
SDA
SA0 - SA2
NC
DU
RESET
Function
Address Inputs
(A12 for 256Mb & 512Mb based modules)
Bank Selects
Data Input/Output
Check Bits (×72 organization only)
Row Address Strobe
Column Address Strobe
Read/Write Input
Clock Enable
SDRAM low data strobes
Differential Clock Input
SDRAM low data mask/
high data strobes
Chip Selects
Power (+2.5 V)
Ground
I/O Driver power supply
VDD Indentification flag
EEPROM power supply
I/O reference supply
Serial bus clock
Serial bus data line
slave address select
no connect
don’t use
Reset pin (forces register inputs low)¹⁾
1) for detailed description of the Power Up and Power Management on DDR Registered DIMMs see the Application Note at
the end of this datasheet
Table 4
Density
2 GB
Address Format
Organization Memory SDRAMs
Ranks
256M x 72 2
(512Mb)
128M × 4
# of
# of row/bank/
SDRAMs column bits
36
13/2/12
(stacked)
Refresh
8k
Period Interval
64 ms 7.8 µs
Data Sheet
8
Rev. 1.02, 2003-12
10282003-P6EY-RWQ2