HYS72D256520GR Datasheet, PDF (16/25 Pages) Infineon Technologies AG – 184 Pin Registered Double Data Rate SDRAM Modules

HYS72D256520GR-7-A
Registered Double Data Rate SDRAM Modules
Electrical Characteristics
Table 10 Electrical Characteristics & AC Timing for DDR components
(for reference only)
70 °C ≤ T_A ≤ 70 °C; V_DDQ = 2.5 V ± 0.2 V; V_DD = 2.5 V ± 0.2 V
Parameter
Symbol DDR266A
–7
min. max.
Active to Read or Write delay
Precharge command period
Active bank A to Active bank B command
Write recovery time
Auto precharge write recovery
+ precharge time
Internal write to read command delay
Exit self-refresh to non-read command
Exit self-refresh to read command
Average Periodic Refresh Interval
512 Mbit
based
t_RCD
t_RP
t_RRD
t_WR
t_DAL
t_WTR
t_XSNR
t_XSRD
t_REFI
20
–
20
–
15
–
15
–
(t_WR/t_CK) +
(t_RP/t_CK)
1
–
75
–
200 –
–
7.8
Unit
ns
ns
ns
ns
t_CK
t_CK
ns
t_CK
µs
Notes
1) to 4)8)
1) to 4)9)
1) to 4)10)
1) to 4)11)
1) to 4)9)
1) to 4)
1) to 4)
1) to 4)
1) to 4)8)
1) Input slew rate >=1V/ns for DDR266.
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is VREF. CK/CK slew rate are >= 1.0 V/ns.
3) Inputs are not recognized as valid until VREF stabilizes.
4) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is
VTT.
5) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
6) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
7) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
8) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
9) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock
cycle time.
10) These parameters guarantee device timing, but they are not necessarily tested on each device
11) Fast slew rate >= 1.0 V/ns , slow slew rate >= 0.5 V/ns and < 1V/ns for command/address and CK & CK slew rate >1.0
V/ns, measured between VOH(ac) and VOL(ac)
Data Sheet
16
Rev. 1.02, 2003-12
10282003-P6EY-RWQ2