HYS72D256520GR Datasheet, PDF (22/25 Pages) Infineon Technologies AG – 184 Pin Registered Double Data Rate SDRAM Modules

HYS72D256520GR-7-A
Registered Double Data Rate SDRAM Modules
Application Note
Power-Up Sequence with RESET — Required
1. The system sets RESET at a valid low level. This is the preferred default state during power-up. This input
condition forces all register outputs to a low state independent of the condition on the register inputs (data and
clock), ensuring that CKE is at a stable low-level at the DDR SDRAMs.
2. The power supplies should be initialized according to the JEDEC-approved initialization sequence for DDR
SDRAMs.
3. Stabilization of Clocks to the SDRAM The system must drive clocks to the application frequency (PLL
operation is not assured until the input clock reaches 20MHz). Stability of clocks at the SDRAMs will be
affected by all applicable system clock devices, and time must be allotted to permit all clock devices to settle.
Once a stable clock is received at the DIMM PLL, the required PLL stabilization time (assuming power to the
DIMM is stable) is 100 microseconds. When a stable clock is present at the SDRAM input (driven from the
PLL), the DDR SDRAM requires 200 µsec prior to SDRAM operation.
4. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM
connector). CKE must be maintained low and all other inputs should be driven to a known state. In general
these commands can be determined by the system designer. One option is to apply an SDRAM ‘NOP’
command (with CKE low), as this is the first command defined by the JEDEC initialization sequence (ideally
this would be a ‘NOP Deselect’ command). A second option is to apply low levels on all of the register inputs
to be consistent with the state of the register outputs.
5. The system switches RESET to a logic ‘high’ level. The SDRAM is now functional and prepared to receive
commands. Since the RESET signal is asynchronous, setting the RESET timing in relation to a specific clock
edge is not required (during this period, register inputs must remain stable).
6. The system must maintain stable register inputs until normal register operation is attained. The registers have
an activation time that allows their clock receivers, data input receivers, and output drivers sufficient time to be
turned on and become stable. During this time the system must maintain the valid logic levels described in step
5. It is also a functional requirement that the registers maintain a low state at the CKE outputs to guarantee
that the DDR SDRAMs continue to receive a low level on CKE. Register activation time (t (ACT) ), from
asynchronous switching of RESET from low to high until the registers are stable and ready to accept an input
signal, is specified in the register and DIMM do-umentation.
7. The system can begin the JEDEC-defined DDR SDRAM power-up sequence (according to the JEDEC-
pproved initialization sequence).
Self Refresh Entry (RESET low, clocks powered off) — Optional
Self Refresh can be used to retain data in DDR SDRAM DIMMs even if the rest of the system is powered down
and the clocks are off. This mode allows the DDR SDRAMs on the DIMM to retain data without external clocking.
Self Refresh mode is an ideal time to utilize the RESET pin, as this can reduce register power consumption
(RESET low deactivates register CK and CK, data input receivers, and data output drivers).
1. The system applies Self Refresh entry command. (CKE→Low, CS→Low, RAS → Low, CAS→ Low, WE→
High)
Note: Note: The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a
Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input
conditions to the SDRAM are Don’t Cares— with the exception of CKE.
2. The system sets RESET at a valid low level. This input condition forces all register outputs to a low state,
independent of the condition on the registerm inputs (data and clock), and ensures that CKE, and all other
control and address signals, are a stable low-level at the DDR SDRAMs. Since the RESET signal is
asynchronous, setting the RESET timing in relation to a specific clock edge is not required.
3. The system turns off clock inputs to the DIMM. (Optional)
a. In order to reduce DIMM PLL current, the clock inputs to the DIMM are turned off, resulting in High-Z clock
inputs to both the SDRAMs and the registers. This must be done after the RESET deactivate time of the
register (t (INACT) ). The deactivate time defines the time in which the clocks and the control and address
Data Sheet
22
Rev. 1.02, 2003-12
10282003-P6EY-RWQ2