HYS72D256520GR Datasheet, PDF (13/25 Pages) Infineon Technologies AG – 184 Pin Registered Double Data Rate SDRAM Modules

HYS72D256520GR-7-A
Registered Double Data Rate SDRAM Modules
Electrical Characteristics
Table 7 Electrical Characteristics and DC Operating Conditions (cont’d)
Parameter
Symbol
Values
Unit Note/Test Condition ¹⁾
Min.
Typ.
Max.
Output Leakage Current I_OZ
–5
Output High Current,
I_OH
—
Normal Strength Driver
5
–16.2
µA DQs are disabled;
0 V ≤ V_OUT ≤ V_DDQ
mA V_OUT = 1.95 V
Output Low
I_OL
16.2
Current, Normal Strength
Driver
—
mA V_OUT = 0.35 V
1) 0 °C ≤ T_A ≤ 70 °C
2) Under all conditions, V_DDQ must be less than or equal to V_DD.
3) Peak to peak AC noise on V_REF may not exceed ± 2% V_{REF (DC)}. V_REF is also expected to track noise variations in V_DDQ.
4) V_TT is not applied directly to the device. V_TT is a system supply for signal termination resistors, is expected to be set equal
to V_REF, and must track variations in the DC level of V_REF.
5) V_ID is the magnitude of the difference between the input level on CK and the input level on CK.
6) The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire
temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the
maximum difference between pull-up and pull-down drivers due to process variation.
7) Inputs are not recognized as valid until V_REF stabilizes.
8) Values are shown per DDR SDRAM component
Table 8 I_DD Conditions
Parameter
Symbol
Operating Current: one bank; active/ precharge; t_RC = t_RCMIN; t_CK = t_CKMIN;
I_DD0
DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once
every two clock cycles.
Operating Current: one bank; active/read/precharge; Burst = 4;
I_DD1
Refer to the following page for detailed test conditions.
Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE ≤ V_ILMAX; t_CK =
t_CKMIN
Precharge Floating Standby Current: CS ≥ V_IHMIN, all banks idle;
CKE ≥ V_IHMIN; t_CK = t_CKMIN, address and other control inputs changing once per clock cycle, V_IN = V_REF
for DQ, DQS and DM.
I_DD2P
I_DD2F
Precharge Quiet Standby Current:
CS ≥ V_IHMIN, all banks idle; CKE ≥ V_IHMIN; t_CK = t_CKMIN, address and other control inputs stable
at ≥ V_IHMIN or ≤ V_ILMAX; V_IN = V_REF for DQ, DQS and DM.
Active Power-Down Standby Current: one bank active; power-down mode;
CKE ≤ V_ILMAX; t_CK = t_CKMIN; V_IN = V_REF for DQ, DQS and DM.
Active Standby Current: one bank active; CS ≥ V_IHMIN; CKE ≥ V_IHMIN; t_RC = t_RASMAX; t_CK = t_CKMIN; DQ,
DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock
cycle.
I_DD2Q
I_DD3P
I_DD3N
Operating Current: one bank active; Burst = 2; reads; continuous burst; address and control inputs
changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200
and DDR266A, CL = 3 for DDR333; t_CK = t_CKMIN; I_OUT = 0 mA
Operating Current: one bank active; Burst = 2; writes; continuous burst; address and control inputs
changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200
and DDR266A, CL = 3 for DDR333; t_CK = t_CKMIN
I_DD4R
I_DD4W
Data Sheet
13
Rev. 1.02, 2003-12
10282003-P6EY-RWQ2