TLE8262-2E Datasheet, PDF (72/94 Pages) Infineon Technologies AG – Universal System Basis Chip

TLE8262-2E
Serial Peripheral Interface
15
Serial Peripheral Interface
15.1
SPI Description
The 16-bit wide Control Input Word is read via the data input SDI, which is synchronized with the clock input CLK
supplied by the microcontroller. The output word appears synchronously at the data output SDO (see Figure 36).
The transmission cycle begins when the chip is selected by the input CSN (Chip Select Not), LOW active. After
the CSN input returns from LOW to HIGH, the word that has been read in becomes the new control word. The
SDO output switches to tri-state status (high impedance) at this point, thereby releasing the SDO bus for other use.
The state of SDI is shifted into the input register with every falling edge on CLK. The state of SDO is shifted out of
the output register after every rising edge on CLK. The number of received input clocks is supervised by a
modulo-16 operation and the Input / Control Word is discarded in case of a mismatch. This error is flagged in the
following SPI output by a “HIGH” at the data output (SDO pin, bit FO) before the first rising edge of the clock is
received. The SPI of the SBC is not daisy chain capable.
CSN high to low: SDO is enabled. Status information transferred to output shift register
CSN
time
CSN low to high: data from shift register is transferred to output functions
CLK
Actual data
SDI
F-I _{0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15}
SDI: will accept data on the falling edge of CLK signal
Actual status
SDO
F-O _{0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15}
SDO: will change state on the rising edge of CLK signal
Figure 36 SPI Data Transfer Timing
time
New data
FI
01
++
time
New status
FO
0
+
1
+
time
15.2
Corrupted data in the SPI data input
When the microcontroller send a wrong SPI command to the SBC, the SBC ignores the information. Wrong SPI
command can be either a number of bits different of 16, the mode selection (MS2..0) = 000 or requesting to go to
an SBC mode which is not allowed by the state machine, for example from SBC Stop Mode to SBC SW Flash
Mode. In that case, an interrupt is generated (if not inhibited) and the bit SPI Fail is set. Since the SPI data is
corrupted, the next SPI output data will remain the former one (the information is then repeated).
Data Sheet
72
Rev. 1.0, 2009-05-26